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linux-davinci
Commit 0676fc12 authored by Linus Torvalds's avatar Linus Torvalds
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Merge master.kernel.org:/home/rmk/linux-2.6-arm

parents 912cbe3c d56c524a
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Showing with 466 additions and 1043 deletions
arch/arm/Kconfig
View file @ 0676fc12
......@@ -704,8 +704,7 @@ source "drivers/acorn/block/Kconfig"
if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
|| ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
|| ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
|| MACH_MP1000
|| ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE
source "drivers/ide/Kconfig"
endif
......
arch/arm/Makefile
View file @ 0676fc12
......@@ -38,6 +38,7 @@ comma = ,
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
arch-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4)
arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
......@@ -143,7 +144,7 @@ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
drivers-$(CONFIG_ARCH_L7200) += drivers/acorn/char/
libs-y += arch/arm/lib/
libs-y := arch/arm/lib/ $(libs-y)
# Default target when executing plain make
ifeq ($(CONFIG_XIP_KERNEL),y)
......
arch/arm/boot/compressed/head.S
View file @ 0676fc12
......@@ -39,8 +39,7 @@
defined(CONFIG_ARCH_IXP4XX) || \
defined(CONFIG_ARCH_IXP2000) || \
defined(CONFIG_ARCH_LH7A40X) || \
defined(CONFIG_ARCH_OMAP) || \
defined(CONFIG_MACH_MP1000)
defined(CONFIG_ARCH_OMAP)
.macro loadsp, rb
addruart \rb
.endm
......
arch/arm/configs/ixdp2401_defconfig
View file @ 0676fc12
......@@ -152,7 +152,7 @@ CONFIG_ALIGNMENT_TRAP=y
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
# CONFIG_XIP_KERNEL is not set
#
......@@ -560,7 +560,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_NR_UARTS=3
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......
arch/arm/configs/ixdp2801_defconfig
View file @ 0676fc12
......@@ -560,7 +560,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_NR_UARTS=3
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......
arch/arm/lib/bitops.h
View file @ 0676fc12
#include <linux/config.h>
#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_MPCORE)
#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_32v6K)
.macro bitop, instr
mov r2, #1
and r3, r0, #7 @ Get bit offset
......
arch/arm/lib/uaccess.S
View file @ 0676fc12
......@@ -43,8 +43,6 @@ ENTRY(__arch_copy_to_user)
stmfd sp!, {r2, r4 - r7, lr}
cmp r2, #4
blt .c2u_not_enough
PLD( pld [r1, #0] )
PLD( pld [r0, #0] )
ands ip, r0, #3
bne .c2u_dest_not_aligned
.c2u_dest_aligned:
......@@ -73,25 +71,13 @@ USER( strt r3, [r0], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #32
blt .c2u_0rem8lp
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
PLD( subs ip, ip, #64 )
PLD( blt .c2u_0cpynopld )
PLD( pld [r1, #60] )
PLD( pld [r0, #60] )
.c2u_0cpy8lp:
PLD( pld [r1, #92] )
PLD( pld [r0, #92] )
.c2u_0cpynopld: ldmia r1!, {r3 - r6}
.c2u_0cpy8lp: ldmia r1!, {r3 - r6}
stmia r0!, {r3 - r6} @ Shouldnt fault
ldmia r1!, {r3 - r6}
subs ip, ip, #32
stmia r0!, {r3 - r6} @ Shouldnt fault
bpl .c2u_0cpy8lp
PLD( cmn ip, #64 )
PLD( bge .c2u_0cpynopld )
PLD( add ip, ip, #64 )
.c2u_0rem8lp: cmn ip, #16
ldmgeia r1!, {r3 - r6}
......@@ -143,17 +129,8 @@ USER( strt r3, [r0], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .c2u_1rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .c2u_1cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.c2u_1cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.c2u_1cpynopld: mov r3, r7, pull #8
.c2u_1cpy8lp: mov r3, r7, pull #8
ldmia r1!, {r4 - r7}
subs ip, ip, #16
orr r3, r3, r4, push #24
......@@ -165,9 +142,6 @@ USER( strt r3, [r0], #4) @ May fault
orr r6, r6, r7, push #24
stmia r0!, {r3 - r6} @ Shouldnt fault
bpl .c2u_1cpy8lp
PLD( cmn ip, #32 )
PLD( bge .c2u_1cpynopld )
PLD( add ip, ip, #32 )
.c2u_1rem8lp: tst ip, #8
movne r3, r7, pull #8
......@@ -210,17 +184,8 @@ USER( strt r3, [r0], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .c2u_2rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .c2u_2cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.c2u_2cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.c2u_2cpynopld: mov r3, r7, pull #16
.c2u_2cpy8lp: mov r3, r7, pull #16
ldmia r1!, {r4 - r7}
subs ip, ip, #16
orr r3, r3, r4, push #16
......@@ -232,9 +197,6 @@ USER( strt r3, [r0], #4) @ May fault
orr r6, r6, r7, push #16
stmia r0!, {r3 - r6} @ Shouldnt fault
bpl .c2u_2cpy8lp
PLD( cmn ip, #32 )
PLD( bge .c2u_2cpynopld )
PLD( add ip, ip, #32 )
.c2u_2rem8lp: tst ip, #8
movne r3, r7, pull #16
......@@ -277,17 +239,8 @@ USER( strt r3, [r0], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .c2u_3rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .c2u_3cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.c2u_3cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.c2u_3cpynopld: mov r3, r7, pull #24
.c2u_3cpy8lp: mov r3, r7, pull #24
ldmia r1!, {r4 - r7}
subs ip, ip, #16
orr r3, r3, r4, push #8
......@@ -299,9 +252,6 @@ USER( strt r3, [r0], #4) @ May fault
orr r6, r6, r7, push #8
stmia r0!, {r3 - r6} @ Shouldnt fault
bpl .c2u_3cpy8lp
PLD( cmn ip, #32 )
PLD( bge .c2u_3cpynopld )
PLD( add ip, ip, #32 )
.c2u_3rem8lp: tst ip, #8
movne r3, r7, pull #24
......@@ -356,8 +306,6 @@ ENTRY(__arch_copy_from_user)
stmfd sp!, {r0, r2, r4 - r7, lr}
cmp r2, #4
blt .cfu_not_enough
PLD( pld [r1, #0] )
PLD( pld [r0, #0] )
ands ip, r0, #3
bne .cfu_dest_not_aligned
.cfu_dest_aligned:
......@@ -385,25 +333,13 @@ USER( ldrt r3, [r1], #4)
sub r2, r2, ip
subs ip, ip, #32
blt .cfu_0rem8lp
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
PLD( subs ip, ip, #64 )
PLD( blt .cfu_0cpynopld )
PLD( pld [r1, #60] )
PLD( pld [r0, #60] )
.cfu_0cpy8lp:
PLD( pld [r1, #92] )
PLD( pld [r0, #92] )
.cfu_0cpynopld: ldmia r1!, {r3 - r6} @ Shouldnt fault
.cfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault
stmia r0!, {r3 - r6}
ldmia r1!, {r3 - r6} @ Shouldnt fault
subs ip, ip, #32
stmia r0!, {r3 - r6}
bpl .cfu_0cpy8lp
PLD( cmn ip, #64 )
PLD( bge .cfu_0cpynopld )
PLD( add ip, ip, #64 )
.cfu_0rem8lp: cmn ip, #16
ldmgeia r1!, {r3 - r6} @ Shouldnt fault
......@@ -456,17 +392,8 @@ USER( ldrt r7, [r1], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .cfu_1rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .cfu_1cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.cfu_1cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.cfu_1cpynopld: mov r3, r7, pull #8
.cfu_1cpy8lp: mov r3, r7, pull #8
ldmia r1!, {r4 - r7} @ Shouldnt fault
subs ip, ip, #16
orr r3, r3, r4, push #24
......@@ -478,9 +405,6 @@ USER( ldrt r7, [r1], #4) @ May fault
orr r6, r6, r7, push #24
stmia r0!, {r3 - r6}
bpl .cfu_1cpy8lp
PLD( cmn ip, #32 )
PLD( bge .cfu_1cpynopld )
PLD( add ip, ip, #32 )
.cfu_1rem8lp: tst ip, #8
movne r3, r7, pull #8
......@@ -523,17 +447,8 @@ USER( ldrt r7, [r1], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .cfu_2rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .cfu_2cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.cfu_2cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.cfu_2cpynopld: mov r3, r7, pull #16
.cfu_2cpy8lp: mov r3, r7, pull #16
ldmia r1!, {r4 - r7} @ Shouldnt fault
subs ip, ip, #16
orr r3, r3, r4, push #16
......@@ -545,9 +460,6 @@ USER( ldrt r7, [r1], #4) @ May fault
orr r6, r6, r7, push #16
stmia r0!, {r3 - r6}
bpl .cfu_2cpy8lp
PLD( cmn ip, #32 )
PLD( bge .cfu_2cpynopld )
PLD( add ip, ip, #32 )
.cfu_2rem8lp: tst ip, #8
movne r3, r7, pull #16
......@@ -590,17 +502,8 @@ USER( ldrt r7, [r1], #4) @ May fault
sub r2, r2, ip
subs ip, ip, #16
blt .cfu_3rem8lp
PLD( pld [r1, #12] )
PLD( pld [r0, #12] )
PLD( subs ip, ip, #32 )
PLD( blt .cfu_3cpynopld )
PLD( pld [r1, #28] )
PLD( pld [r0, #28] )
.cfu_3cpy8lp:
PLD( pld [r1, #44] )
PLD( pld [r0, #44] )
.cfu_3cpynopld: mov r3, r7, pull #24
.cfu_3cpy8lp: mov r3, r7, pull #24
ldmia r1!, {r4 - r7} @ Shouldnt fault
orr r3, r3, r4, push #8
mov r4, r4, pull #24
......@@ -612,9 +515,6 @@ USER( ldrt r7, [r1], #4) @ May fault
stmia r0!, {r3 - r6}
subs ip, ip, #16
bpl .cfu_3cpy8lp
PLD( cmn ip, #32 )
PLD( bge .cfu_3cpynopld )
PLD( add ip, ip, #32 )
.cfu_3rem8lp: tst ip, #8
movne r3, r7, pull #24
......
arch/arm/mach-clps711x/Kconfig
View file @ 0676fc12
......@@ -69,17 +69,6 @@ config EP72XX_ROM_BOOT
You almost surely want to say N here.
config MACH_MP1000
bool "MACH_MP1000"
help
Say Y if you intend to run the kernel on the Comdial MP1000 platform.
config MP1000_90MHZ
bool "MP1000_90MHZ"
depends on MACH_MP1000
help
Say Y if you have the MP1000 configured to be set at 90MHZ rather than 74MHZ
endmenu
endif
arch/arm/mach-clps711x/Makefile
View file @ 0676fc12
......@@ -15,7 +15,6 @@ obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o
obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
obj-$(CONFIG_MACH_MP1000) += mp1000-mach.o mp1000-mm.o mp1000-seprom.o
obj-$(CONFIG_ARCH_P720T) += p720t.o
leds-$(CONFIG_ARCH_P720T) += p720t-leds.o
obj-$(CONFIG_LEDS) += $(leds-y)
arch/arm/mach-clps711x/edb7211-mm.c
View file @ 0676fc12
......@@ -55,22 +55,22 @@ static struct map_desc edb7211_io_desc[] __initdata = {
.virtual = EP7211_VIRT_EXTKBD,
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
.length = SZ_1M,
.type - MT_DEVICE
.type = MT_DEVICE,
}, { /* and CS8900A Ethernet chip */
.virtual = EP7211_VIRT_CS8900A,
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE
.type = MT_DEVICE,
}, { /* flash banks */
.virtual = EP7211_VIRT_FLASH1,
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
.length = SZ_8M,
.type = MT_DEVICE
.type = MT_DEVICE,
}, {
.virtual = EP7211_VIRT_FLASH2,
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
.length = SZ_8M,
.type = MT_DEVICE
.type = MT_DEVICE,
}
};
......
arch/arm/mach-clps711x/mp1000-mach.c deleted 100644 → 0
View file @ 912cbe3c
/*
* linux/arch/arm/mach-mp1000/mp1000.c
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/mp1000-seprom.h>
#include "common.h"
extern void mp1000_map_io(void);
static void __init mp1000_init(void)
{
seprom_init();
}
MACHINE_START(MP1000, "Comdial MP1000")
/* Maintainer: Jon Ringle */
.phys_ram = 0xc0000000,
.phys_io = 0x80000000,
.io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
.boot_params = 0xc0015100,
.map_io = mp1000_map_io,
.init_irq = clps711x_init_irq,
.init_machine = mp1000_init,
.timer = &clps711x_timer,
MACHINE_END
arch/arm/mach-clps711x/mp1000-mm.c deleted 100644 → 0
View file @ 912cbe3c
/*
* linux/arch/arm/mach-mp1000/mm.c
*
* Extra MM routines for the MP1000
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
extern void clps711x_map_io(void);
static struct map_desc mp1000_io_desc[] __initdata = {
{ MP1000_EIO_BASE, MP1000_EIO_START, MP1000_EIO_SIZE, MT_DEVICE },
{ MP1000_FIO_BASE, MP1000_FIO_START, MP1000_FIO_SIZE, MT_DEVICE },
{ MP1000_LIO_BASE, MP1000_LIO_START, MP1000_LIO_SIZE, MT_DEVICE },
{ MP1000_NIO_BASE, MP1000_NIO_START, MP1000_NIO_SIZE, MT_DEVICE },
{ MP1000_IDE_BASE, MP1000_IDE_START, MP1000_IDE_SIZE, MT_DEVICE },
{ MP1000_DSP_BASE, MP1000_DSP_START, MP1000_DSP_SIZE, MT_DEVICE }
};
void __init mp1000_map_io(void)
{
clps711x_map_io();
iotable_init(mp1000_io_desc, ARRAY_SIZE(mp1000_io_desc));
}
arch/arm/mach-clps711x/mp1000-seprom.c deleted 100644 → 0
View file @ 912cbe3c
/*`
* mp1000-seprom.c
*
* This file contains the Serial EEPROM code for the MP1000 board
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/hardware/clps7111.h>
#include <asm/arch/mp1000-seprom.h>
/* If SepromInit() can initialize and checksum the seprom successfully, */
/* then it will point seprom_data_ptr at the shadow copy. */
static eeprom_struct seprom_data; /* shadow copy of seprom content */
eeprom_struct *seprom_data_ptr = 0; /* 0 => not initialized */
/*
* Port D Bit 5 is Chip Select for EEPROM
* Port E Bit 0 is Input, Data out from EEPROM
* Port E Bit 1 is Output, Data in to EEPROM
* Port E Bit 2 is Output, CLK to EEPROM
*/
static char *port_d_ptr = (char *)(CLPS7111_VIRT_BASE + PDDR);
static char *port_e_ptr = (char *)(CLPS7111_VIRT_BASE + PEDR);
#define NO_OF_SHORTS 64 // Device is 64 x 16 bits
#define ENABLE_RW 0
#define DISABLE_RW 1
static inline void toggle_seprom_clock(void)
{
*port_e_ptr |= HwPortESepromCLK;
*port_e_ptr &= ~(HwPortESepromCLK);
}
static inline void select_eeprom(void)
{
*port_d_ptr |= HwPortDEECS;
*port_e_ptr &= ~(HwPortESepromCLK);
}
static inline void deselect_eeprom(void)
{
*port_d_ptr &= ~(HwPortDEECS);
*port_e_ptr &= ~(HwPortESepromDIn);
}
/*
* GetSepromDataPtr - returns pointer to shadow (RAM) copy of seprom
* and returns 0 if seprom is not initialized or
* has a checksum error.
*/
eeprom_struct* get_seprom_ptr(void)
{
return seprom_data_ptr;
}
unsigned char* get_eeprom_mac_address(void)
{
return seprom_data_ptr->variant.eprom_struct.mac_Address;
}
/*
* ReadSProm, Physically reads data from the Serial PROM
*/
static void read_sprom(short address, int length, eeprom_struct *buffer)
{
short data = COMMAND_READ | (address & 0x3F);
short bit;
int i;
select_eeprom();
// Clock in 9 bits of the command
for (i = 0, bit = 0x100; i < 9; i++, bit >>= 1) {
if (data & bit)
*port_e_ptr |= HwPortESepromDIn;
else
*port_e_ptr &= ~(HwPortESepromDIn);
toggle_seprom_clock();
}
//
// Now read one or more shorts of data from the Seprom
//
while (length-- > 0) {
data = 0;
// Read 16 bits at a time
for (i = 0; i < 16; i++) {
data <<= 1;
toggle_seprom_clock();
data |= *port_e_ptr & HwPortESepromDOut;
}
buffer->variant.eprom_short_data[address++] = data;
}
deselect_eeprom();
return;
}
/*
* ReadSerialPROM
*
* Input: Pointer to array of 64 x 16 Bits
*
* Output: if no problem reading data is filled in
*/
static void read_serial_prom(eeprom_struct *data)
{
read_sprom(0, 64, data);
}
//
// Compute Serial EEPROM checksum
//
// Input: Pointer to struct with Eprom data
//
// Output: The computed Eprom checksum
//
static short compute_seprom_checksum(eeprom_struct *data)
{
short checksum = 0;
int i;
for (i = 0; i < 126; i++) {
checksum += (short)data->variant.eprom_byte_data[i];
}
return((short)(0x5555 - (checksum & 0xFFFF)));
}
//
// Make sure the data port bits for the SEPROM are correctly initialised
//
void __init seprom_init(void)
{
short checksum;
// Init Port D
*(char *)(CLPS7111_VIRT_BASE + PDDDR) = 0x0;
*(char *)(CLPS7111_VIRT_BASE + PDDR) = 0x15;
// Init Port E
*(int *)(CLPS7111_VIRT_BASE + PEDDR) = 0x06;
*(int *)(CLPS7111_VIRT_BASE + PEDR) = 0x04;
//
// Make sure that EEPROM struct size never exceeds 128 bytes
//
if (sizeof(eeprom_struct) > 128) {
panic("Serial PROM struct size > 128, aborting read\n");
}
read_serial_prom(&seprom_data);
checksum = compute_seprom_checksum(&seprom_data);
if (checksum != seprom_data.variant.eprom_short_data[63]) {
panic("Serial EEPROM checksum failed\n");
}
seprom_data_ptr = &seprom_data;
}
arch/arm/mach-ixp2000/core.c
View file @ 0676fc12
......@@ -402,6 +402,40 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}
/*
* Error interrupts. These are used extensively by the microengine drivers
*/
static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{
int i;
unsigned long status = *IXP2000_IRQ_ERR_STATUS;
for(i = 31; i >= 0; i--) {
if(status & (1 << i)) {
desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
}
}
}
static void ixp2000_err_irq_mask(unsigned int irq)
{
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}
static void ixp2000_err_irq_unmask(unsigned int irq)
{
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}
static struct irqchip ixp2000_err_irq_chip = {
.ack = ixp2000_err_irq_mask,
.mask = ixp2000_err_irq_mask,
.unmask = ixp2000_err_irq_unmask
};
static struct irqchip ixp2000_pci_irq_chip = {
.ack = ixp2000_pci_irq_mask,
.mask = ixp2000_pci_irq_mask,
......@@ -459,6 +493,18 @@ void __init ixp2000_init_irq(void)
} else set_irq_flags(irq, 0);
}
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
IXP2000_VALID_ERR_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_err_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID);
}
else
set_irq_flags(irq, 0);
}
set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
/*
* GPIO IRQs are invalid until someone sets the interrupt mode
* by calling set_irq_type().
......
arch/arm/mach-ixp2000/enp2611.c
View file @ 0676fc12
......@@ -69,19 +69,19 @@ static struct sys_timer enp2611_timer = {
static struct map_desc enp2611_io_desc[] __initdata = {
{
.virtual = ENP2611_CALEB_VIRT_BASE,
.physical = ENP2611_CALEB_PHYS_BASE,
.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
.length = ENP2611_CALEB_SIZE,
.type = MT_IXP2000_DEVICE
.type = MT_IXP2000_DEVICE,
}, {
.virtual = ENP2611_PM3386_0_VIRT_BASE,
.physical = ENP2611_PM3386_0_PHYS_BASE,
.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
.length = ENP2611_PM3386_0_SIZE,
.type = MT_IXP2000_DEVICE
.type = MT_IXP2000_DEVICE,
}, {
.virtual = ENP2611_PM3386_1_VIRT_BASE,
.physical = ENP2611_PM3386_1_PHYS_BASE,
.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
.length = ENP2611_PM3386_1_SIZE,
.type = MT_IXP2000_DEVICE
.type = MT_IXP2000_DEVICE,
}
};
......
arch/arm/mach-pxa/lubbock.c
View file @ 0676fc12
......@@ -19,16 +19,20 @@
#include <linux/major.h>
#include <linux/fb.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/hardware/sa1111.h>
......@@ -199,10 +203,75 @@ static struct platform_device smc91x_device = {
.resource = smc91x_resources,
};
static struct resource flash_resources[] = {
[0] = {
.start = 0x00000000,
.end = SZ_64M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x04000000,
.end = 0x04000000 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
},
};
static struct mtd_partition lubbock_partitions[] = {
{
.name = "Bootloader",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
},{
.name = "Kernel",
.size = 0x00100000,
.offset = 0x00040000,
},{
.name = "Filesystem",
.size = MTDPART_SIZ_FULL,
.offset = 0x00140000
}
};
static struct flash_platform_data lubbock_flash_data[2] = {
{
.map_name = "cfi_probe",
.parts = lubbock_partitions,
.nr_parts = ARRAY_SIZE(lubbock_partitions),
}, {
.map_name = "cfi_probe",
.parts = NULL,
.nr_parts = 0,
}
};
static struct platform_device lubbock_flash_device[2] = {
{
.name = "pxa2xx-flash",
.id = 0,
.dev = {
.platform_data = &lubbock_flash_data[0],
},
.resource = &flash_resources[0],
.num_resources = 1,
},
{
.name = "pxa2xx-flash",
.id = 1,
.dev = {
.platform_data = &lubbock_flash_data[1],
},
.resource = &flash_resources[1],
.num_resources = 1,
},
};
static struct platform_device *devices[] __initdata = {
&sa1111_device,
&lub_audio_device,
&smc91x_device,
&lubbock_flash_device[0],
&lubbock_flash_device[1],
};
static struct pxafb_mach_info sharp_lm8v31 __initdata = {
......@@ -315,10 +384,21 @@ static struct pxaficp_platform_data lubbock_ficp_platform_data = {
static void __init lubbock_init(void)
{
int flashboot = (LUB_CONF_SWITCHES & 1);
pxa_set_udc_info(&udc_info);
set_pxa_fb_info(&sharp_lm8v31);
pxa_set_mci_info(&lubbock_mci_platform_data);
pxa_set_ficp_info(&lubbock_ficp_platform_data);
lubbock_flash_data[0].width = lubbock_flash_data[1].width =
(BOOT_DEF & 1) ? 2 : 4;
/* Compensate for the nROMBT switch which swaps the flash banks */
printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
flashboot?"Flash":"ROM", flashboot);
lubbock_flash_data[flashboot^1].name = "application-flash";
lubbock_flash_data[flashboot].name = "boot-rom";
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
......
arch/arm/mach-pxa/mainstone.c
View file @ 0676fc12
......@@ -20,6 +20,9 @@
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <asm/types.h>
#include <asm/setup.h>
......@@ -27,10 +30,12 @@
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mainstone.h>
......@@ -190,6 +195,69 @@ static struct platform_device mst_audio_device = {
.dev = { .platform_data = &mst_audio_ops },
};
static struct resource flash_resources[] = {
[0] = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_64M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PXA_CS1_PHYS,
.end = PXA_CS1_PHYS + SZ_64M - 1,
.flags = IORESOURCE_MEM,
},
};
static struct mtd_partition mainstoneflash0_partitions[] = {
{
.name = "Bootloader",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
},{
.name = "Kernel",
.size = 0x00400000,
.offset = 0x00040000,
},{
.name = "Filesystem",
.size = MTDPART_SIZ_FULL,
.offset = 0x00440000
}
};
static struct flash_platform_data mst_flash_data[2] = {
{
.map_name = "cfi_probe",
.parts = mainstoneflash0_partitions,
.nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
}, {
.map_name = "cfi_probe",
.parts = NULL,
.nr_parts = 0,
}
};
static struct platform_device mst_flash_device[2] = {
{
.name = "pxa2xx-flash",
.id = 0,
.dev = {
.platform_data = &mst_flash_data[0],
},
.resource = &flash_resources[0],
.num_resources = 1,
},
{
.name = "pxa2xx-flash",
.id = 1,
.dev = {
.platform_data = &mst_flash_data[1],
},
.resource = &flash_resources[1],
.num_resources = 1,
},
};
static void mainstone_backlight_power(int on)
{
if (on) {
......@@ -318,16 +386,34 @@ static struct pxaficp_platform_data mainstone_ficp_platform_data = {
.transceiver_mode = mainstone_irda_transceiver_mode,
};
static struct platform_device *platform_devices[] __initdata = {
&smc91x_device,
&mst_audio_device,
&mst_flash_device[0],
&mst_flash_device[1],
};
static void __init mainstone_init(void)
{
int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
mst_flash_data[1].width = 4;
/* Compensate for SW7 which swaps the flash banks */
mst_flash_data[SW7].name = "processor-flash";
mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
mst_flash_data[0].name);
/*
* On Mainstone, we route AC97_SYSCLK via GPIO45 to
* the audio daughter card
*/
pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
platform_device_register(&smc91x_device);
platform_device_register(&mst_audio_device);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
/* reading Mainstone's "Virtual Configuration Register"
might be handy to select LCD type here */
......
arch/arm/mm/Kconfig
View file @ 0676fc12
......@@ -250,6 +250,18 @@ config CPU_V6
select CPU_COPY_V6
select CPU_TLB_V6
# ARMv6k
config CPU_32v6K
bool "Support ARM V6K processor extensions" if !SMP
depends on CPU_V6
default y if SMP
help
Say Y here if your ARMv6 processor supports the 'K' extension.
This enables the kernel to use some instructions not present
on previous processors, and as such a kernel build with this
enabled will not boot on processors with do not support these
instructions.
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
......
arch/arm/mm/mm-armv.c
View file @ 0676fc12
......@@ -469,14 +469,14 @@ void __init create_mapping(struct map_desc *md)
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
printk(KERN_WARNING "BUG: not creating mapping for "
"0x%016llx at 0x%08lx in user region\n",
"0x%08llx at 0x%08lx in user region\n",
__pfn_to_phys((u64)md->pfn), md->virtual);
return;
}
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
printk(KERN_WARNING "BUG: mapping for 0x%016llx at 0x%08lx "
printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
"overlaps vmalloc space\n",
__pfn_to_phys((u64)md->pfn), md->virtual);
}
......@@ -492,14 +492,14 @@ void __init create_mapping(struct map_desc *md)
if(md->pfn >= 0x100000) {
if(domain) {
printk(KERN_ERR "MM: invalid domain in supersection "
"mapping for 0x%016llx at 0x%08lx\n",
"mapping for 0x%08llx at 0x%08lx\n",
__pfn_to_phys((u64)md->pfn), md->virtual);
return;
}
if((md->virtual | md->length | __pfn_to_phys(md->pfn))
& ~SUPERSECTION_MASK) {
printk(KERN_ERR "MM: cannot create mapping for "
"0x%016llx at 0x%08lx invalid alignment\n",
"0x%08llx at 0x%08lx invalid alignment\n",
__pfn_to_phys((u64)md->pfn), md->virtual);
return;
}
......
drivers/char/nvram.c
View file @ 0676fc12
......@@ -32,11 +32,9 @@
* added changelog
* 1.2 Erik Gilling: Cobalt Networks support
* Tim Hockin: general cleanup, Cobalt support
* 1.3 Jon Ringle: Comdial MP1000 support
*
*/
#define NVRAM_VERSION "1.3"
#define NVRAM_VERSION "1.2"
#include <linux/module.h>
#include <linux/config.h>
......@@ -47,7 +45,6 @@
#define PC 1
#define ATARI 2
#define COBALT 3
#define MP1000 4
/* select machine configuration */
#if defined(CONFIG_ATARI)
......@@ -57,9 +54,6 @@
# if defined(CONFIG_COBALT)
# include <linux/cobalt-nvram.h>
# define MACH COBALT
# elif defined(CONFIG_MACH_MP1000)
# undef MACH
# define MACH MP1000
# else
# define MACH PC
# endif
......@@ -118,23 +112,6 @@
#endif
#if MACH == MP1000
/* RTC in a MP1000 */
#define CHECK_DRIVER_INIT() 1
#define MP1000_CKS_RANGE_START 0
#define MP1000_CKS_RANGE_END 111
#define MP1000_CKS_LOC 112
#define NVRAM_BYTES (128-NVRAM_FIRST_BYTE)
#define mach_check_checksum mp1000_check_checksum
#define mach_set_checksum mp1000_set_checksum
#define mach_proc_infos mp1000_proc_infos
#endif
/* Note that *all* calls to CMOS_READ and CMOS_WRITE must be done with
* rtc_lock held. Due to the index-port/data-port design of the RTC, we
* don't want two different things trying to get to it at once. (e.g. the
......@@ -938,91 +915,6 @@ atari_proc_infos(unsigned char *nvram, char *buffer, int *len,
#endif /* MACH == ATARI */
#if MACH == MP1000
static int
mp1000_check_checksum(void)
{
int i;
unsigned short sum = 0;
unsigned short expect;
for (i = MP1000_CKS_RANGE_START; i <= MP1000_CKS_RANGE_END; ++i)
sum += __nvram_read_byte(i);
expect = __nvram_read_byte(MP1000_CKS_LOC+1)<<8 |
__nvram_read_byte(MP1000_CKS_LOC);
return ((sum & 0xffff) == expect);
}
static void
mp1000_set_checksum(void)
{
int i;
unsigned short sum = 0;
for (i = MP1000_CKS_RANGE_START; i <= MP1000_CKS_RANGE_END; ++i)
sum += __nvram_read_byte(i);
__nvram_write_byte(sum >> 8, MP1000_CKS_LOC + 1);
__nvram_write_byte(sum & 0xff, MP1000_CKS_LOC);
}
#ifdef CONFIG_PROC_FS
#define SERVER_N_LEN 32
#define PATH_N_LEN 32
#define FILE_N_LEN 32
#define NVRAM_MAGIC_SIG 0xdead
typedef struct NvRamImage
{
unsigned short int magic;
unsigned short int mode;
char fname[FILE_N_LEN];
char path[PATH_N_LEN];
char server[SERVER_N_LEN];
char pad[12];
} NvRam;
static int
mp1000_proc_infos(unsigned char *nvram, char *buffer, int *len,
off_t *begin, off_t offset, int size)
{
int checksum;
NvRam* nv = (NvRam*)nvram;
spin_lock_irq(&rtc_lock);
checksum = __nvram_check_checksum();
spin_unlock_irq(&rtc_lock);
PRINT_PROC("Checksum status: %svalid\n", checksum ? "" : "not ");
switch( nv->mode )
{
case 0 :
PRINT_PROC( "\tMode 0, tftp prompt\n" );
break;
case 1 :
PRINT_PROC( "\tMode 1, booting from disk\n" );
break;
case 2 :
PRINT_PROC( "\tMode 2, Alternate boot from disk /boot/%s\n", nv->fname );
break;
case 3 :
PRINT_PROC( "\tMode 3, Booting from net:\n" );
PRINT_PROC( "\t\t%s:%s%s\n",nv->server, nv->path, nv->fname );
break;
default:
PRINT_PROC( "\tInconsistant nvram?\n" );
break;
}
return 1;
}
#endif
#endif /* MACH == MP1000 */
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(__nvram_read_byte);
......
drivers/net/Kconfig
View file @ 0676fc12
......@@ -1374,7 +1374,7 @@ config FORCEDETH
config CS89x0
tristate "CS89x0 support"
depends on (NET_PCI && (ISA || ARCH_IXDP2X01)) || ARCH_PNX0105 || MACH_MP1000
depends on (NET_PCI && (ISA || ARCH_IXDP2X01)) || ARCH_PNX0105
---help---
Support for CS89x0 chipset based Ethernet cards. If you have a
network (Ethernet) card of this type, say Y and read the
......
drivers/net/cs89x0.c
View file @ 0676fc12
......@@ -182,10 +182,6 @@ static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0};
#define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */
static unsigned int netcard_portlist[] __initdata = {CIRRUS_DEFAULT_BASE, 0};
static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0};
#elif defined(CONFIG_MACH_MP1000)
#include <asm/arch/mp1000-seprom.h>
static unsigned int netcard_portlist[] __initdata = {MP1000_EIO_BASE+0x300, 0};
static unsigned int cs8900_irq_map[] = {IRQ_EINT3,0,0,0};
#else
static unsigned int netcard_portlist[] __initdata =
{ 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
......@@ -594,10 +590,6 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
cnt -= j;
}
} else
#elif defined(CONFIG_MACH_MP1000)
if (1) {
memcpy(dev->dev_addr, get_eeprom_mac_address(), ETH_ALEN);
} else
#endif
if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) ==
......@@ -657,10 +649,6 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
if (1) {
printk(KERN_NOTICE "cs89x0: No EEPROM on HiCO.SH4\n");
} else
#elif defined(CONFIG_MACH_MP1000)
if (1) {
lp->force |= FORCE_RJ45;
} else
#endif
if ((readreg(dev, PP_SelfST) & EEPROM_PRESENT) == 0)
printk(KERN_WARNING "cs89x0: No EEPROM, relying on command line....\n");
......@@ -1243,7 +1231,7 @@ net_open(struct net_device *dev)
else
#endif
{
#if !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX0105) && !defined(CONFIG_MACH_MP1000)
#if !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX0105)
if (((1 << dev->irq) & lp->irq_map) == 0) {
printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n",
dev->name, dev->irq, lp->irq_map);
......
drivers/net/cs89x0.h
View file @ 0676fc12
......@@ -16,7 +16,7 @@
#include <linux/config.h>
#if defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX0105) || defined (CONFIG_MACH_MP1000)
#if defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX0105)
/* IXDP2401/IXDP2801 uses dword-aligned register addressing */
#define CS89x0_PORT(reg) ((reg) * 2)
#else
......
drivers/serial/clps711x.c
View file @ 0676fc12
......@@ -408,11 +408,7 @@ static struct uart_port clps711x_ports[UART_NR] = {
{
.iobase = SYSCON1,
.irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
#ifdef CONFIG_MP1000_90MHZ
.uartclk = 4515840,
#else
.uartclk = 3686400,
#endif
.fifosize = 16,
.ops = &clps711x_pops,
.line = 0,
......@@ -421,11 +417,7 @@ static struct uart_port clps711x_ports[UART_NR] = {
{
.iobase = SYSCON2,
.irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
#ifdef CONFIG_MP1000_90MHZ
.uartclk = 4515840,
#else
.uartclk = 3686400,
#endif
.fifosize = 16,
.ops = &clps711x_pops,
.line = 1,
......@@ -559,7 +551,6 @@ console_initcall(clps711xuart_console_init);
static struct uart_driver clps711x_reg = {
.driver_name = "ttyCL",
.dev_name = "ttyCL",
.devfs_name = "ttyCL",
.major = SERIAL_CLPS711X_MAJOR,
.minor = SERIAL_CLPS711X_MINOR,
.nr = UART_NR,
......
include/asm-arm/arch-clps711x/hardware.h
View file @ 0676fc12
......@@ -235,121 +235,4 @@
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#if defined (CONFIG_MACH_MP1000)
/* NOR FLASH */
#define MP1000_NIO_BASE 0xf9000000 /* virtual */
#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
#define MP1000_NIO_SIZE 0x00400000
/* DSP Interface */
#define MP1000_DSP_BASE 0xfa000000 /* virtual */
#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
#define MP1000_DSP_SIZE 0x00100000
/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
#define MP1000_LIO_BASE 0xfb000000 /* virtual */
#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
#define MP1000_LIO_SIZE 0x00100000
/* NAND FLASH */
#define MP1000_FIO_BASE 0xfc000000 /* virtual */
#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
#define MP1000_FIO_SIZE 0x00800000
/* Ethernet */
#define MP1000_EIO_BASE 0xfd000000 /* virtual */
#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
#define MP1000_EIO_SIZE 0x00100000
#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
/* IDE */
#define MP1000_IDE_BASE 0xfe000000 /* virtual */
#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
#define IRQ_HARDDISK IRQ_EINT2
/*
* IDE registers definition
*/
#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
#define IDE_BASE_OFF (MP1000_IDE_BASE)
#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
#define IDE_IRQ IRQ_EINT2
#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
#define RTC_ALWAYS_BCD 0
/*
// Definitions of the bit fields in the HwPortA register for the
// MP1000 board.
*/
#define HwPortAKeyboardRow1 0x00000001
#define HwPortAKeyboardRow2 0x00000002
#define HwPortAKeyboardRow3 0x00000004
#define HwPortAKeyboardRow4 0x00000008
#define HwPortAKeyboardRow5 0x00000010
#define HwPortAKeyboardRow6 0x00000020
#define HwPortALCDEnable 0x00000040
#define HwPortAOffhook 0x00000080
/*
// Definitions of the bit fields in the HwPortB register for the
// MP1000 board.
*/
#define HwPortBL3Mode 0x00000001
#define HwPortBL3Clk 0x00000002
#define HwPortBSClk 0x00000001
#define HwPortBSData 0x00000002
#define HwPortBL3Data 0x00000004
#define HwPortBMute 0x00000008
#define HwPortBQD0 0x00000010
#define HwPortBQD1 0x00000020
#define HwPortBQD2 0x00000040
#define HwPortBQD3 0x00000080
/*
// Definitions of the bit fields in the HwPortD register for the
// MP1000 board.
*/
#define HwPortDLED1 0x00000001
#define HwPortDLED2 0x00000002
#define HwPortDLED3 0x00000004
#define HwPortDLED4 0x00000008
#define HwPortDLED5 0x00000010
#define HwPortDEECS 0x00000020
#define HwPortBRTS 0x00000040
#define HwPortBRI 0x00000080
/*
// Definitions of the bit fields in the HwPortE register for the
// MP1000 board.
*/
#define HwPortECLE 0x00000001
#define HwPortESepromDOut 0x00000001
#define HwPortEALE 0x00000002
#define HwPortESepromDIn 0x00000002
#define HwPortENANDCS 0x00000004
#define HwPortESepromCLK 0x00000004
#endif // #if defined (CONFIG_MACH_MP1000)
#endif
include/asm-arm/arch-clps711x/mp1000-seprom.h deleted 100644 → 0
View file @ 912cbe3c
#ifndef MP1000_SEPROM_H
#define MP1000_SEPROM_H
/*
* mp1000-seprom.h
*
*
* This file contains the Serial EEPROM definitions for the MP1000 board
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define COMMAND_ERASE (0x1C0)
#define COMMAND_ERASE_ALL (0x120)
#define COMMAND_WRITE_DISABLE (0x100)
#define COMMAND_WRITE_ENABLE (0x130)
#define COMMAND_READ (0x180)
#define COMMAND_WRITE (0x140)
#define COMMAND_WRITE_ALL (0x110)
//
// Serial EEPROM data format
//
#define PACKED __attribute__ ((packed))
typedef struct _EEPROM {
union {
unsigned char eprom_byte_data[128];
unsigned short eprom_short_data[64];
struct {
unsigned char version PACKED; // EEPROM Version "1" for now
unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc)
unsigned char major_hw_version PACKED; // Major Hardware version (Hex)
unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex)
unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number
unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD)
unsigned char country PACKED; // Country of deployment
unsigned char mac_Address[6] PACKED; // MAC Address
unsigned char oem_string[20] PACKED; // OEM ID string
unsigned short feature_bits1 PACKED; // Feature Bits 1
unsigned short feature_bits2 PACKED; // Feature Bits 2
unsigned char filler[75] PACKED; // Unused/Undefined 0 initialized
unsigned short checksum PACKED; // byte accumulated short checksum
} eprom_struct;
} variant;
} eeprom_struct;
/* These settings must be mutually exclusive */
#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */
#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */
#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */
#define FEATURE_BITS1_CPUIS90MEG 0x0010
extern void seprom_init(void);
extern eeprom_struct* get_seprom_ptr(void);
extern unsigned char* get_eeprom_mac_address(void);
#endif /* MP1000_SEPROM_H */
include/asm-arm/arch-iop3xx/iop321.h
View file @ 0676fc12
......@@ -40,7 +40,7 @@
#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1)
/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
#define IOP321_PCI_LOWER_MEM_PA 0x80000000
#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
......
include/asm-arm/arch-ixp2000/irqs.h
View file @ 0676fc12
......@@ -67,12 +67,45 @@
#define IRQ_IXP2000_PCIA 40
#define IRQ_IXP2000_PCIB 41
#define NR_IXP2000_IRQS 42
/* Int sources from IRQ_ERROR_STATUS */
#define IRQ_IXP2000_DRAM0_MIN_ERR 42
#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
#define IRQ_IXP2000_DRAM1_MIN_ERR 44
#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
#define IRQ_IXP2000_DRAM2_MIN_ERR 46
#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
/* 48-57 reserved */
#define IRQ_IXP2000_SRAM0_ERR 58
#define IRQ_IXP2000_SRAM1_ERR 59
#define IRQ_IXP2000_SRAM2_ERR 60
#define IRQ_IXP2000_SRAM3_ERR 61
/* 62-65 reserved */
#define IRQ_IXP2000_MEDIA_ERR 66
#define IRQ_IXP2000_PCI_ERR 67
#define IRQ_IXP2000_SP_INT 68
#define NR_IXP2000_IRQS 69
#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
#define IXP2000_VALID_ERR_IRQ_MASK (\
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
/*
* This allows for all the on-chip sources plus up to 32 CPLD based
* IRQs. Should be more than enough.
......
include/asm-arm/mmu_context.h
View file @ 0676fc12
......@@ -86,7 +86,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
cpu_set(cpu, next->cpu_vm_mask);
check_context(next);
cpu_switch_mm(next->pgd, next);
cpu_clear(cpu, prev->cpu_vm_mask);
if (cache_is_vivt())
cpu_clear(cpu, prev->cpu_vm_mask);
}
}
......
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