• eric miao's avatar
    [ARM] pxa: use new pin configuration mechanism for mainstone · fef06d27
    eric miao authored
    1. the following code to configure PGSRx is no way portable and
       intuitive:
    
    -	PGSR0 = 0x00008800;
    -       PGSR1 = 0x00000002;
    -       PGSR2 = 0x0001FC00;
    -       PGSR3 = 0x00001F81;
    
       this is removed as low power state has already been encoded in
       the pin configuration definitions.
    
       Note: there is no specific reason for some of the GPIOs to drive
       high in low power mode as indicated by the above setting, those
       bits are ignored, and the result is validated to work.
    
    2. the following code to configure GPIO wakeup is removed as this
       is now totally handled by pxa2xx_mfp_config():
    
    -       PWER  = 0xC0000002;
    -       PRER  = 0x00000002;
    -       PFER  = 0x00000002;
    Signed-off-by: default avatareric miao <eric.miao@marvell.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    fef06d27
mainstone.c 13.9 KB