• H. Peter Anvin's avatar
    x86: Disable large pages on CPUs with Atom erratum AAE44 · 7a0fc404
    H. Peter Anvin authored
    Atom erratum AAE44/AAF40/AAG38/AAH41:
    
    "If software clears the PS (page size) bit in a present PDE (page
    directory entry), that will cause linear addresses mapped through this
    PDE to use 4-KByte pages instead of using a large page after old TLB
    entries are invalidated. Due to this erratum, if a code fetch uses
    this PDE before the TLB entry for the large page is invalidated then
    it may fetch from a different physical address than specified by
    either the old large page translation or the new 4-KByte page
    translation. This erratum may also cause speculative code fetches from
    incorrect addresses."
    
    [http://download.intel.com/design/processor/specupdt/319536.pdf]
    
    Where as commit 211b3d03 seems to
    workaround errata AAH41 (mixed 4K TLBs) it reduces the window of
    opportunity for the bug to occur and does not totally remove it.  This
    patch disables mixed 4K/4MB page tables totally avoiding the page
    splitting and not tripping this processor issue.
    
    This is based on an original patch by Colin King.
    Originally-by: default avatarColin Ian King <colin.king@canonical.com>
    Cc: Colin Ian King <colin.king@canonical.com>
    Cc: Ingo Molnar <mingo@elte.hu>
    Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
    LKML-Reference: <1269271251-19775-1-git-send-email-colin.king@canonical.com>
    Cc: <stable@kernel.org>
    7a0fc404
intel.c 13.6 KB