• Dan Williams's avatar
    ioat3: interrupt coalescing · b9cc9869
    Dan Williams authored
    The hardware automatically disables further interrupts after each event
    until rearmed.  This allows a delay to be injected between the occurence
    of the interrupt and the running of the cleanup routine.  The delay is
    scaled by the descriptor backlog and then written to the INTRDELAY
    register which specifies the number of microseconds to hold off
    interrupt delivery after an interrupt event occurs.  According to
    powertop this reduces the interrupt rate from ~5000 intr/s to ~150
    intr/s per without affecting throughput (simple dd to a raid6 array).
    Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
    b9cc9869
dma_v3.c 36.9 KB