• Russell King's avatar
    [ARM] Fix ASID version switch · b5ac7bd4
    Russell King authored
    Close a hole in the ASID version switch, particularly the following
    scenario:
    
    CPU0 MM PID			CPU1 MM PID
    	idle
    				  A	pid(A)
    				  A	idle(lazy tlb)
    		* new asid version triggered by B *
      B	pid(B)
      A	pid(A)
    		* MM A gets new asid version *
      A	idle(lazy tlb)
    				  A	pid(A)
    		* CPU1 doesn't see the new ASID *
    
    The result is that CPU1 continues running with the hardware set
    for the original (stale) ASID value, but mm->context.id contains
    the new ASID value.  The result is that the next MM fault on CPU1
    updates the page table entries, but flush_tlb_page() fails due to
    wrong ASID.
    
    There is a related case with a threaded application is allocated
    a new ASID on one CPU while another of its threads is running on
    some different CPU.  This scenario is not fixed by this commit.
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    b5ac7bd4
context.c 1.45 KB