• Shinya Kuribayashi's avatar
    MIPS: NEC VR5500 processor support fixup · a644b277
    Shinya Kuribayashi authored
    Current VR5500 processor support lacks of some functions which are
    expected to be configured/synthesized on arch initialization.
    
    Here're some VR5500A spec notes:
    
    * All execution hazards are handled in hardware.
    
    * Once VR5500A stops the operation of the pipeline by WAIT instruction,
      it could return from the standby mode only when either a reset, NMI
      request, or all enabled interrupts is/are detected.  In other words,
      if interrupts are disabled by Status.IE=0, it keeps in standby mode
      even when interrupts are internally asserted.
    
      Notes on WAIT: The operation of the processor is undefined if WAIT
      insn is in the branch delay slot.  The operation is also undefined
      if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.
    
    * VR5500A core only implements the Load prefetch.
    
    With these changes, it boots fine.
    Signed-off-by: default avatarShinya Kuribayashi <shinya.kuribayashi@necel.com>
    Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    a644b277
prefetch.h 2.1 KB