This patch implements enable/disable for non-CORE DPLLs (DPLLs 1, 2,
4, 5) in the OMAP34xx clock framework.

"Enabling" a DPLL in this context means taking the DPLL from off to
lock, off to bypass, or bypass to lock.  If the clock's target rate is
set to the DPLL parent's clock rate, the DPLL will go to bypass.
Otherwise, the DPLL will attempt to lock.  "Disabling" means going
from bypass or lock to off.

Jouni Högander contributed a fix for _omap3_noncore_dpll_lock().to
bypass the DPLL state test when the DPLL is in autoidle mode.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>