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Haojian Zhuang authored
In PXA3xx SoC family, V_CORE power doamin is supplied by BUCK1 that is controller by ADTV1 or ADTV2 register. By default, v1 and v2 has the same copy. If v1 or v2 is updated, the last value that is written to either register takes effect. It means that v1 and v2 has different copy. And the actual voltage output is determinated by last update on either register. DA9034/35 is binded with PXA3xx SoC family. While SoC is scaling OP or entering/exiting lower power mode, SoC needs to change voltage of V_CORE power doamin. In order to be efficient, POWER I2C (hardcode) mode could be enabled in SoC. In this mode, SoC will control v2 register directly. In original DA903x driver, software will only read regulator data from v1 register. But SoC controls v2 register directly. It results that v1 and v2 isn't synchronized. Wrong data will be read from v1 register. So access v2 register in da903x driver instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
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