A redundant PLL divisior update for the I2S master clock after AV core
firmware load was missed in earlier PLL parameter changes.  This one really
doesn't matter because it's redundant and gets overwritten, but the driver
should be self consistent in the values used.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>