Most DPLLs use sys_clk as their bypass rate source.  But DPLL1 and DPLL2
use high-frequency bypass clocks dpll1_fclk and dpll2_fclk as their parents
during bypass.  Add a new struct dpll_data field to track the DPLL's bypass
source clock.

Kevin Hilman <khilman@deeprootsystems.com> helped catch this - thanks Kevin.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>