• Paul Walmsley's avatar
    OMAP3 clock: optimize DPLL rate rounding algorithm · 6f6d82bb
    Paul Walmsley authored
    The previous DPLL rate rounding algorithm counted the divider (N) down
    from the maximum to 1.  Since we currently use a broad DPLL rate
    tolerance, and lower N values are more power-efficient, we can often
    bypass several iterations through the loop by counting N upwards from
    1.
    
    Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several
    test cycles of this patch - thanks Peter.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    6f6d82bb
clock.c 27.3 KB