The MPC83xx SPI controller clock divider can divide the system clock by not
more then 1024.  The spi_mpc83xx driver does not check this and silently
writes garbage to the SPI controller registers when asked to run at lower
frequencies.  I've tried to run the SPI on a 266MHz MPC8349E with 100kHz
for debugging a bus problem and suddenly was confronted with a 2nd problem
to debug..  ;-)

The patch adds an additional check which avoids writing garbage to the SPI
controller registers and warn the user about it.  This might help others to
avoid simmilar problems.

Cc: Kumar Gala <galak@gate.crashing.org>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>