According to the ARM11MPCore Erratum 351422 (r0p0), under extremely
rare conditions, in an MPCore node consisting of at least 3 CPUs, two
CPUs trying to perform a STREX to data on the same shared cache line
can enter a livelock situation. This patch adds variable spinning time
to the locking routines.
Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>