Starting with ARMv6, accesses to strongly ordered memory are not
guaranteed to complete before a subsequent instruction modifying the
interrupt mask in CPSR. This can cause potential problems with masking
or acknowledging an IRQ at the device or interrupt controller level
followed by a local_irq_enable or local_irq_restore (see B2.4.3 in ARM
ARM revI). This patch adds a DSB after masking the interrupts at the
interrupt controller level to ensure that the strongly ordered memory
access was completed.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>