• Ralf Baechle's avatar
    [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts. · 30e748a5
    Ralf Baechle authored
    This matters to any sort of device that is wired to one of the CPU
    interrupt pins on an SMP system.  Typically the scenario is most easily
    triggered with the count/compare timer interrupt where the same interrupt
    number and thus irq_desc is used on each processor.
    
       CPU A			CPU B
    
       do_IRQ()
       generic_handle_irq()
       handle_level_irq()
       spin_lock(desc_lock)
       set IRQ_INPROGRESS
       spin_unlock(desc_lock)
    				do_IRQ()
    				generic_handle_irq()
    				handle_level_irq()
    				spin_lock(desc_lock)
    				IRQ_INPROGRESS set => bail out
       spin_lock(desc_lock)
       clear IRQ_INPROGRESS
       spin_unlock(desc_lock)
    
    In case of the cp0 compare interrupt this means the interrupt will be
    acked and not handled or re-armed on CPU b, so there won't be any timer
    interrupt until the count register wraps around.
    
    With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
    working right on VSMP because the count registers are synchronized on
    bootup so it takes something that disables interrupts for a long time on
    one processor to trigger this one.
    
    For scenarios where an interrupt is multicasted or broadcasted over several
    CPUs the existing code was safe and the fix will break it.  There is no
    way to know in the interrupt controller code because it is abstracted from
    the platform code.  I think we do not have such a setup currently, so this
    should be ok.
    Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    30e748a5
irq_cpu.c 3.22 KB