Here's a another pass at better modeling of clocks and PLLs.  The
longer term goal being the ability model the clock tree well enough to
do DVFS on devices that support it.

  - generalize PLL control and clock distribution
  - model PLLs, their dividers and the resulting PLL-derived clocks
  - add clock parent/child relationships
  - drop 'div_by_*' in favor of using PLL dividers
  - misc. other minor cleanups
  - move clock definitions into chip-specific code
  - start using clk_get_rate() to get rates (UART, timers)
  - drop DM*_CLOCK_TICK_RATE

Updates from last version

  - multiple updates and fixes from David Brownell (Thanks!)
  - use of divider registers instead of 'fixed_divisor' field
    to better model PLL-derived clocks based on divider regs.
  - drop some hard-coded LPSC init in favor of enabling with
    relevant clock.

TODO:
- seek-and-destroy hardcoded clock rates
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>