A read / write cycle is defined by tw0 + tw1. It was wrongly assumed that
the 1 cycle long CS active edge to read / write active edge is part of
each cycle, thus we ended up with too low tw1 value -> too short cycle
time.
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>