cx24123.c 27.1 KB
Newer Older
1 2 3 4 5
/*
    Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver

    Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>

6 7
    Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>

#include "dvb_frontend.h"
#include "cx24123.h"

32 33
#define XTAL 10111000

34
static int force_band;
35 36 37 38 39 40
static int debug;
#define dprintk(args...) \
	do { \
		if (debug) printk (KERN_DEBUG "cx24123: " args); \
	} while (0)

41 42
struct cx24123_state
{
43 44 45 46 47 48 49 50 51 52 53 54 55
	struct i2c_adapter* i2c;
	const struct cx24123_config* config;

	struct dvb_frontend frontend;

	u32 lastber;
	u16 snr;

	/* Some PLL specifics for tuning */
	u32 VCAarg;
	u32 VGAarg;
	u32 bandselectarg;
	u32 pllarg;
56
	u32 FILTune;
57 58 59 60 61 62

	/* The Demod/Tuner can't easily provide these, we cache them */
	u32 currentfreq;
	u32 currentsymbolrate;
};

63 64 65 66 67 68 69
/* Various tuner defaults need to be established for a given symbol rate Sps */
static struct
{
	u32 symbolrate_low;
	u32 symbolrate_high;
	u32 VCAprogdata;
	u32 VGAprogdata;
70
	u32 FILTune;
71 72 73 74 75
} cx24123_AGC_vals[] =
{
	{
		.symbolrate_low		= 1000000,
		.symbolrate_high	= 4999999,
76 77
		/* the specs recommend other values for VGA offsets,
		   but tests show they are wrong */
78 79 80
		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,
		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x07,
		.FILTune		= 0x27f /* 0.41 V */
81 82 83 84
	},
	{
		.symbolrate_low		=  5000000,
		.symbolrate_high	= 14999999,
85 86
		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,
		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x1f,
87
		.FILTune		= 0x317 /* 0.90 V */
88 89 90 91
	},
	{
		.symbolrate_low		= 15000000,
		.symbolrate_high	= 45000000,
92 93 94
		.VGAprogdata		= (1 << 19) | (0x100 << 9) | 0x180,
		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x3f,
		.FILTune		= 0x145 /* 2.70 V */
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
	},
};

/*
 * Various tuner defaults need to be established for a given frequency kHz.
 * fixme: The bounds on the bands do not match the doc in real life.
 * fixme: Some of them have been moved, other might need adjustment.
 */
static struct
{
	u32 freq_low;
	u32 freq_high;
	u32 VCOdivider;
	u32 progdata;
} cx24123_bandselect_vals[] =
{
111
	/* band 1 */
112 113 114 115
	{
		.freq_low	= 950000,
		.freq_high	= 1074999,
		.VCOdivider	= 4,
116
		.progdata	= (0 << 19) | (0 << 9) | 0x40,
117
	},
118 119

	/* band 2 */
120 121
	{
		.freq_low	= 1075000,
122 123 124
		.freq_high	= 1177999,
		.VCOdivider	= 4,
		.progdata	= (0 << 19) | (0 << 9) | 0x80,
125
	},
126 127

	/* band 3 */
128
	{
129 130
		.freq_low	= 1178000,
		.freq_high	= 1295999,
131
		.VCOdivider	= 2,
132
		.progdata	= (0 << 19) | (1 << 9) | 0x01,
133
	},
134 135

	/* band 4 */
136
	{
137 138
		.freq_low	= 1296000,
		.freq_high	= 1431999,
139
		.VCOdivider	= 2,
140
		.progdata	= (0 << 19) | (1 << 9) | 0x02,
141
	},
142 143

	/* band 5 */
144
	{
145 146
		.freq_low	= 1432000,
		.freq_high	= 1575999,
147
		.VCOdivider	= 2,
148
		.progdata	= (0 << 19) | (1 << 9) | 0x04,
149
	},
150 151

	/* band 6 */
152
	{
153
		.freq_low	= 1576000,
154 155
		.freq_high	= 1717999,
		.VCOdivider	= 2,
156
		.progdata	= (0 << 19) | (1 << 9) | 0x08,
157
	},
158 159

	/* band 7 */
160 161 162 163
	{
		.freq_low	= 1718000,
		.freq_high	= 1855999,
		.VCOdivider	= 2,
164
		.progdata	= (0 << 19) | (1 << 9) | 0x10,
165
	},
166 167

	/* band 8 */
168 169 170 171
	{
		.freq_low	= 1856000,
		.freq_high	= 2035999,
		.VCOdivider	= 2,
172
		.progdata	= (0 << 19) | (1 << 9) | 0x20,
173
	},
174 175

	/* band 9 */
176 177
	{
		.freq_low	= 2036000,
178
		.freq_high	= 2150000,
179
		.VCOdivider	= 2,
180
		.progdata	= (0 << 19) | (1 << 9) | 0x40,
181 182 183
	},
};

184 185 186 187 188 189 190
static struct {
	u8 reg;
	u8 data;
} cx24123_regdata[] =
{
	{0x00, 0x03}, /* Reset system */
	{0x00, 0x00}, /* Clear reset */
191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
	{0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
	{0x04, 0x10}, /* MPEG */
	{0x05, 0x04}, /* MPEG */
	{0x06, 0x31}, /* MPEG (default) */
	{0x0b, 0x00}, /* Freq search start point (default) */
	{0x0c, 0x00}, /* Demodulator sample gain (default) */
	{0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */
	{0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
	{0x0f, 0xfe}, /* FEC search mask (all supported codes) */
	{0x10, 0x01}, /* Default search inversion, no repeat (default) */
	{0x16, 0x00}, /* Enable reading of frequency */
	{0x17, 0x01}, /* Enable EsNO Ready Counter */
	{0x1c, 0x80}, /* Enable error counter */
	{0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
	{0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
	{0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
	{0x29, 0x00}, /* DiSEqC LNB_DC off */
	{0x2a, 0xb0}, /* DiSEqC Parameters (default) */
	{0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
	{0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
211 212 213 214 215
	{0x2d, 0x00},
	{0x2e, 0x00},
	{0x2f, 0x00},
	{0x30, 0x00},
	{0x31, 0x00},
216 217
	{0x32, 0x8c}, /* DiSEqC Parameters (default) */
	{0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
218
	{0x34, 0x00},
219 220 221 222 223 224 225 226 227 228
	{0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
	{0x36, 0x02}, /* DiSEqC Parameters (default) */
	{0x37, 0x3a}, /* DiSEqC Parameters (default) */
	{0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
	{0x44, 0x00}, /* Constellation (default) */
	{0x45, 0x00}, /* Symbol count (default) */
	{0x46, 0x0d}, /* Symbol rate estimator on (default) */
	{0x56, 0x41}, /* Various (default) */
	{0x57, 0xff}, /* Error Counter Window (default) */
	{0x67, 0x83}, /* Non-DCII symbol clock */
229 230 231 232 233 234 235 236
};

static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
{
	u8 buf[] = { reg, data };
	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
	int err;

237 238 239 240
	if (debug>1)
		printk("cx24123: %s:  write reg 0x%02x, value 0x%02x\n",
						__FUNCTION__,reg, data);

241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266
	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
		printk("%s: writereg error(err == %i, reg == 0x%02x,"
			 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
		return -EREMOTEIO;
	}

	return 0;
}

static int cx24123_readreg(struct cx24123_state* state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = {
		{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
		{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
	};

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
		return ret;
	}

267 268 269
	if (debug>1)
		printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);

270 271 272 273 274
	return b1[0];
}

static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
{
275 276 277
	u8 nom_reg = cx24123_readreg(state, 0x0e);
	u8 auto_reg = cx24123_readreg(state, 0x10);

278 279
	switch (inversion) {
	case INVERSION_OFF:
280
		dprintk("%s:  inversion off\n",__FUNCTION__);
281 282
		cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
		cx24123_writereg(state, 0x10, auto_reg | 0x80);
283 284
		break;
	case INVERSION_ON:
285
		dprintk("%s:  inversion on\n",__FUNCTION__);
286 287
		cx24123_writereg(state, 0x0e, nom_reg | 0x80);
		cx24123_writereg(state, 0x10, auto_reg | 0x80);
288 289
		break;
	case INVERSION_AUTO:
290
		dprintk("%s:  inversion auto\n",__FUNCTION__);
291
		cx24123_writereg(state, 0x10, auto_reg & ~0x80);
292 293 294 295 296 297 298 299 300 301 302 303 304 305
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
{
	u8 val;

	val = cx24123_readreg(state, 0x1b) >> 7;

306 307
	if (val == 0) {
		dprintk("%s:  read inversion off\n",__FUNCTION__);
308
		*inversion = INVERSION_OFF;
309 310
	} else {
		dprintk("%s:  read inversion on\n",__FUNCTION__);
311
		*inversion = INVERSION_ON;
312
	}
313 314 315 316 317 318

	return 0;
}

static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
{
319 320
	u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;

321
	if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
322
		fec = FEC_AUTO;
323 324 325

	switch (fec) {
	case FEC_1_2:
326
		dprintk("%s:  set FEC to 1/2\n",__FUNCTION__);
327 328 329
		cx24123_writereg(state, 0x0e, nom_reg | 0x01);
		cx24123_writereg(state, 0x0f, 0x02);
		break;
330
	case FEC_2_3:
331
		dprintk("%s:  set FEC to 2/3\n",__FUNCTION__);
332 333 334
		cx24123_writereg(state, 0x0e, nom_reg | 0x02);
		cx24123_writereg(state, 0x0f, 0x04);
		break;
335
	case FEC_3_4:
336
		dprintk("%s:  set FEC to 3/4\n",__FUNCTION__);
337 338 339 340
		cx24123_writereg(state, 0x0e, nom_reg | 0x03);
		cx24123_writereg(state, 0x0f, 0x08);
		break;
	case FEC_4_5:
341
		dprintk("%s:  set FEC to 4/5\n",__FUNCTION__);
342 343 344 345
		cx24123_writereg(state, 0x0e, nom_reg | 0x04);
		cx24123_writereg(state, 0x0f, 0x10);
		break;
	case FEC_5_6:
346
		dprintk("%s:  set FEC to 5/6\n",__FUNCTION__);
347 348 349 350 351 352 353 354 355 356 357 358 359
		cx24123_writereg(state, 0x0e, nom_reg | 0x05);
		cx24123_writereg(state, 0x0f, 0x20);
		break;
	case FEC_6_7:
		dprintk("%s:  set FEC to 6/7\n",__FUNCTION__);
		cx24123_writereg(state, 0x0e, nom_reg | 0x06);
		cx24123_writereg(state, 0x0f, 0x40);
		break;
	case FEC_7_8:
		dprintk("%s:  set FEC to 7/8\n",__FUNCTION__);
		cx24123_writereg(state, 0x0e, nom_reg | 0x07);
		cx24123_writereg(state, 0x0f, 0x80);
		break;
360
	case FEC_AUTO:
361
		dprintk("%s:  set FEC to auto\n",__FUNCTION__);
362 363
		cx24123_writereg(state, 0x0f, 0xfe);
		break;
364 365 366
	default:
		return -EOPNOTSUPP;
	}
367 368

	return 0;
369 370 371 372
}

static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
{
373
	int ret;
374

375 376 377
	ret = cx24123_readreg (state, 0x1b);
	if (ret < 0)
		return ret;
378 379 380
	ret = ret & 0x07;

	switch (ret) {
381
	case 1:
382 383
		*fec = FEC_1_2;
		break;
384
	case 2:
385 386
		*fec = FEC_2_3;
		break;
387
	case 3:
388 389
		*fec = FEC_3_4;
		break;
390
	case 4:
391 392
		*fec = FEC_4_5;
		break;
393
	case 5:
394 395
		*fec = FEC_5_6;
		break;
396 397 398
	case 6:
		*fec = FEC_6_7;
		break;
399
	case 7:
400 401
		*fec = FEC_7_8;
		break;
402
	default:
403 404
		/* this can happen when there's no lock */
		*fec = FEC_NONE;
405 406
	}

407
	return 0;
408 409
}

410 411 412 413 414 415 416 417 418 419 420 421 422 423 424
/* Approximation of closest integer of log2(a/b). It actually gives the
   lowest integer i such that 2^i >= round(a/b) */
static u32 cx24123_int_log2(u32 a, u32 b)
{
	u32 exp, nearest = 0;
	u32 div = a / b;
	if(a % b >= b / 2) ++div;
	if(div < (1 << 31))
	{
		for(exp = 1; div > exp; nearest++)
			exp += exp;
	}
	return nearest;
}

425 426
static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
{
427
	u32 tmp, sample_rate, ratio, sample_gain;
428 429 430
	u8 pll_mult;

	/*  check if symbol rate is within limits */
431 432
	if ((srate > state->frontend.ops.info.symbol_rate_max) ||
	    (srate < state->frontend.ops.info.symbol_rate_min))
433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455
		return -EOPNOTSUPP;;

	/* choose the sampling rate high enough for the required operation,
	   while optimizing the power consumed by the demodulator */
	if (srate < (XTAL*2)/2)
		pll_mult = 2;
	else if (srate < (XTAL*3)/2)
		pll_mult = 3;
	else if (srate < (XTAL*4)/2)
		pll_mult = 4;
	else if (srate < (XTAL*5)/2)
		pll_mult = 5;
	else if (srate < (XTAL*6)/2)
		pll_mult = 6;
	else if (srate < (XTAL*7)/2)
		pll_mult = 7;
	else if (srate < (XTAL*8)/2)
		pll_mult = 8;
	else
		pll_mult = 9;


	sample_rate = pll_mult * XTAL;
456

457 458
	/*
	    SYSSymbolRate[21:0] = (srate << 23) / sample_rate
459

460 461 462 463 464
	    We have to use 32 bit unsigned arithmetic without precision loss.
	    The maximum srate is 45000000 or 0x02AEA540. This number has
	    only 6 clear bits on top, hence we can shift it left only 6 bits
	    at a time. Borrowed from cx24110.c
	*/
465

466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484
	tmp = srate << 6;
	ratio = tmp / sample_rate;

	tmp = (tmp % sample_rate) << 6;
	ratio = (ratio << 6) + (tmp / sample_rate);

	tmp = (tmp % sample_rate) << 6;
	ratio = (ratio << 6) + (tmp / sample_rate);

	tmp = (tmp % sample_rate) << 5;
	ratio = (ratio << 5) + (tmp / sample_rate);


	cx24123_writereg(state, 0x01, pll_mult * 6);

	cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
	cx24123_writereg(state, 0x09, (ratio >>  8) & 0xff );
	cx24123_writereg(state, 0x0a, (ratio      ) & 0xff );

485 486 487 488 489 490
	/* also set the demodulator sample gain */
	sample_gain = cx24123_int_log2(sample_rate, srate);
	tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
	cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);

	dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);
491 492 493 494 495 496 497 498 499 500 501

	return 0;
}

/*
 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
 * and the correct band selected. Calculate those values
 */
static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct cx24123_state *state = fe->demodulator_priv;
502 503
	u32 ndiv = 0, adiv = 0, vco_div = 0;
	int i = 0;
504
	int pump = 2;
505 506
	int band = 0;
	int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]);
507 508 509 510 511 512 513

	/* Defaults for low freq, low rate */
	state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
	state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
	state->bandselectarg = cx24123_bandselect_vals[0].progdata;
	vco_div = cx24123_bandselect_vals[0].VCOdivider;

514
	/* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
515
	for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
516 517
	{
		if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
518
		    (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
519 520
			state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
			state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
521
			state->FILTune = cx24123_AGC_vals[i].FILTune;
522 523 524
		}
	}

525 526
	/* determine the band to use */
	if(force_band < 1 || force_band > num_bands)
527
	{
528 529 530 531 532
		for (i = 0; i < num_bands; i++)
		{
			if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
			    (cx24123_bandselect_vals[i].freq_high >= p->frequency) )
				band = i;
533 534
		}
	}
535 536 537 538 539 540 541 542 543 544 545
	else
		band = force_band - 1;

	state->bandselectarg = cx24123_bandselect_vals[band].progdata;
	vco_div = cx24123_bandselect_vals[band].VCOdivider;

	/* determine the charge pump current */
	if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 )
		pump = 0x01;
	else
		pump = 0x02;
546 547

	/* Determine the N/A dividers for the requested lband freq (in kHz). */
548 549 550
	/* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
	ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
	adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
551 552

	if (adiv == 0)
553
		ndiv++;
554

555 556
	/* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
	state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
557 558 559 560 561 562 563 564 565 566 567

	return 0;
}

/*
 * Tuner data is 21 bits long, must be left-aligned in data.
 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
 */
static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
{
	struct cx24123_state *state = fe->demodulator_priv;
568
	unsigned long timeout;
569

570 571
	dprintk("%s:  pll writereg called, data=0x%08x\n",__FUNCTION__,data);

572 573 574 575 576 577 578
	/* align the 21 bytes into to bit23 boundary */
	data = data << 3;

	/* Reset the demod pll word length to 0x15 bits */
	cx24123_writereg(state, 0x21, 0x15);

	/* write the msb 8 bits, wait for the send to be completed */
579
	timeout = jiffies + msecs_to_jiffies(40);
580
	cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
581 582 583
	while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
		if (time_after(jiffies, timeout)) {
			printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
584 585
			return -EREMOTEIO;
		}
586
		msleep(10);
587 588 589
	}

	/* send another 8 bytes, wait for the send to be completed */
590
	timeout = jiffies + msecs_to_jiffies(40);
591
	cx24123_writereg(state, 0x22, (data>>8) & 0xff );
592 593 594
	while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
		if (time_after(jiffies, timeout)) {
			printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
595 596
			return -EREMOTEIO;
		}
597
		msleep(10);
598 599 600
	}

	/* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
601
	timeout = jiffies + msecs_to_jiffies(40);
602
	cx24123_writereg(state, 0x22, (data) & 0xff );
603 604 605
	while ((cx24123_readreg(state, 0x20) & 0x80)) {
		if (time_after(jiffies, timeout)) {
			printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
606 607
			return -EREMOTEIO;
		}
608
		msleep(10);
609 610 611 612 613 614 615 616 617 618 619 620
	}

	/* Trigger the demod to configure the tuner */
	cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
	cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);

	return 0;
}

static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct cx24123_state *state = fe->demodulator_priv;
621 622 623
	u8 val;

	dprintk("frequency=%i\n", p->frequency);
624

625
	if (cx24123_pll_calculate(fe, p) != 0) {
626 627 628 629 630 631 632 633 634 635 636 637
		printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
		return -EINVAL;
	}

	/* Write the new VCO/VGA */
	cx24123_pll_writereg(fe, p, state->VCAarg);
	cx24123_pll_writereg(fe, p, state->VGAarg);

	/* Write the new bandselect and pll args */
	cx24123_pll_writereg(fe, p, state->bandselectarg);
	cx24123_pll_writereg(fe, p, state->pllarg);

638 639 640 641 642
	/* set the FILTUNE voltage */
	val = cx24123_readreg(state, 0x28) & ~0x3;
	cx24123_writereg(state, 0x27, state->FILTune >> 2);
	cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));

643 644 645
	dprintk("%s:  pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
			state->bandselectarg,state->pllarg);

646 647 648 649 650 651 652 653
	return 0;
}

static int cx24123_initfe(struct dvb_frontend* fe)
{
	struct cx24123_state *state = fe->demodulator_priv;
	int i;

654 655
	dprintk("%s:  init frontend\n",__FUNCTION__);

656
	/* Configure the demod to a good set of defaults */
657
	for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
658 659 660 661 662 663 664 665 666 667
		cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);

	return 0;
}

static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
{
	struct cx24123_state *state = fe->demodulator_priv;
	u8 val;

668
	val = cx24123_readreg(state, 0x29) & ~0x40;
669

670 671 672 673 674 675 676 677 678 679
	switch (voltage) {
	case SEC_VOLTAGE_13:
		dprintk("%s: setting voltage 13V\n", __FUNCTION__);
		return cx24123_writereg(state, 0x29, val | 0x80);
	case SEC_VOLTAGE_18:
		dprintk("%s: setting voltage 18V\n", __FUNCTION__);
		return cx24123_writereg(state, 0x29, val & 0x7f);
	default:
		return -EINVAL;
	};
680 681

	return 0;
682 683
}

684 685 686 687 688 689 690 691 692 693 694 695 696
/* wait for diseqc queue to become ready (or timeout) */
static void cx24123_wait_for_diseqc(struct cx24123_state *state)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(200);
	while (!(cx24123_readreg(state, 0x29) & 0x40)) {
		if(time_after(jiffies, timeout)) {
			printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
			break;
		}
		msleep(10);
	}
}

697
static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
698
{
699
	struct cx24123_state *state = fe->demodulator_priv;
700
	int i, val, tone;
701 702

	dprintk("%s:\n",__FUNCTION__);
703

704 705 706 707
	/* stop continuous tone if enabled */
	tone = cx24123_readreg(state, 0x29);
	if (tone & 0x10)
		cx24123_writereg(state, 0x29, tone & ~0x50);
708

709 710 711
	/* wait for diseqc queue ready */
	cx24123_wait_for_diseqc(state);

712
	/* select tone mode */
713
	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
714 715 716 717 718 719 720

	for (i = 0; i < cmd->msg_len; i++)
		cx24123_writereg(state, 0x2C + i, cmd->msg[i]);

	val = cx24123_readreg(state, 0x29);
	cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));

721 722
	/* wait for diseqc message to finish sending */
	cx24123_wait_for_diseqc(state);
723

724 725 726 727 728
	/* restart continuous tone if enabled */
	if (tone & 0x10) {
		cx24123_writereg(state, 0x29, tone & ~0x40);
	}

729 730 731 732 733 734
	return 0;
}

static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
{
	struct cx24123_state *state = fe->demodulator_priv;
735
	int val, tone;
736 737 738

	dprintk("%s:\n", __FUNCTION__);

739 740 741 742
	/* stop continuous tone if enabled */
	tone = cx24123_readreg(state, 0x29);
	if (tone & 0x10)
		cx24123_writereg(state, 0x29, tone & ~0x50);
743

744
	/* wait for diseqc queue ready */
745 746
	cx24123_wait_for_diseqc(state);

747
	/* select tone mode */
748 749
	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
	msleep(30);
750 751 752 753 754 755 756 757
	val = cx24123_readreg(state, 0x29);
	if (burst == SEC_MINI_A)
		cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
	else if (burst == SEC_MINI_B)
		cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
	else
		return -EINVAL;

758
	cx24123_wait_for_diseqc(state);
759
	cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
760

761 762 763 764
	/* restart continuous tone if enabled */
	if (tone & 0x10) {
		cx24123_writereg(state, 0x29, tone & ~0x40);
	}
765
	return 0;
766 767 768 769 770 771 772 773 774 775 776
}

static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
	struct cx24123_state *state = fe->demodulator_priv;

	int sync = cx24123_readreg(state, 0x14);
	int lock = cx24123_readreg(state, 0x20);

	*status = 0;
	if (lock & 0x01)
777 778 779
		*status |= FE_HAS_SIGNAL;
	if (sync & 0x02)
		*status |= FE_HAS_CARRIER;
780 781 782
	if (sync & 0x04)
		*status |= FE_HAS_VITERBI;
	if (sync & 0x08)
783
		*status |= FE_HAS_SYNC;
784
	if (sync & 0x80)
785
		*status |= FE_HAS_LOCK;
786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817

	return 0;
}

/*
 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
 * is available, so this value doubles up to satisfy both measurements
 */
static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct cx24123_state *state = fe->demodulator_priv;

	state->lastber =
		((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
		(cx24123_readreg(state, 0x1d) << 8 |
		cx24123_readreg(state, 0x1e));

	/* Do the signal quality processing here, it's derived from the BER. */
	/* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
	if (state->lastber < 5000)
		state->snr = 655*100;
	else if ( (state->lastber >=   5000) && (state->lastber <  55000) )
		state->snr = 655*90;
	else if ( (state->lastber >=  55000) && (state->lastber < 150000) )
		state->snr = 655*80;
	else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
		state->snr = 655*70;
	else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
		state->snr = 655*65;
	else
		state->snr = 0;

818 819
	dprintk("%s:  BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr);

820 821 822 823 824 825 826 827 828 829
	*ber = state->lastber;

	return 0;
}

static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
	struct cx24123_state *state = fe->demodulator_priv;
	*signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */

830 831
	dprintk("%s:  Signal strength = %d\n",__FUNCTION__,*signal_strength);

832 833 834 835 836 837 838 839
	return 0;
}

static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct cx24123_state *state = fe->demodulator_priv;
	*snr = state->snr;

840 841
	dprintk("%s:  read S/N index = %d\n",__FUNCTION__,*snr);

842 843 844 845 846 847 848 849
	return 0;
}

static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct cx24123_state *state = fe->demodulator_priv;
	*ucblocks = state->lastber;

850 851
	dprintk("%s:  ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks);

852 853 854 855 856 857 858
	return 0;
}

static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct cx24123_state *state = fe->demodulator_priv;

859 860
	dprintk("%s:  set_frontend\n",__FUNCTION__);

861 862 863 864
	if (state->config->set_ts_params)
		state->config->set_ts_params(fe, 0);

	state->currentfreq=p->frequency;
865
	state->currentsymbolrate = p->u.qpsk.symbol_rate;
866 867 868 869 870 871 872

	cx24123_set_inversion(state, p->inversion);
	cx24123_set_fec(state, p->u.qpsk.fec_inner);
	cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
	cx24123_pll_tune(fe, p);

	/* Enable automatic aquisition and reset cycle */
873
	cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
874 875 876 877 878 879 880 881 882 883
	cx24123_writereg(state, 0x00, 0x10);
	cx24123_writereg(state, 0x00, 0);

	return 0;
}

static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct cx24123_state *state = fe->demodulator_priv;

884 885
	dprintk("%s:  get_frontend\n",__FUNCTION__);

886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904
	if (cx24123_get_inversion(state, &p->inversion) != 0) {
		printk("%s: Failed to get inversion status\n",__FUNCTION__);
		return -EREMOTEIO;
	}
	if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
		printk("%s: Failed to get fec status\n",__FUNCTION__);
		return -EREMOTEIO;
	}
	p->frequency = state->currentfreq;
	p->u.qpsk.symbol_rate = state->currentsymbolrate;

	return 0;
}

static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
{
	struct cx24123_state *state = fe->demodulator_priv;
	u8 val;

905 906
	/* wait for diseqc queue ready */
	cx24123_wait_for_diseqc(state);
907

908
	val = cx24123_readreg(state, 0x29) & ~0x40;
909

910 911 912 913 914 915 916 917 918 919
	switch (tone) {
	case SEC_TONE_ON:
		dprintk("%s: setting tone on\n", __FUNCTION__);
		return cx24123_writereg(state, 0x29, val | 0x10);
	case SEC_TONE_OFF:
		dprintk("%s: setting tone off\n",__FUNCTION__);
		return cx24123_writereg(state, 0x29, val & 0xef);
	default:
		printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
		return -EINVAL;
920
	}
921 922

	return 0;
923 924 925 926 927 928 929 930 931 932 933
}

static void cx24123_release(struct dvb_frontend* fe)
{
	struct cx24123_state* state = fe->demodulator_priv;
	dprintk("%s\n",__FUNCTION__);
	kfree(state);
}

static struct dvb_frontend_ops cx24123_ops;

934 935
struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
				    struct i2c_adapter* i2c)
936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968
{
	struct cx24123_state* state = NULL;
	int ret;

	dprintk("%s\n",__FUNCTION__);

	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
	if (state == NULL) {
		printk("Unable to kmalloc\n");
		goto error;
	}

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->lastber = 0;
	state->snr = 0;
	state->VCAarg = 0;
	state->VGAarg = 0;
	state->bandselectarg = 0;
	state->pllarg = 0;
	state->currentfreq = 0;
	state->currentsymbolrate = 0;

	/* check if the demod is there */
	ret = cx24123_readreg(state, 0x00);
	if ((ret != 0xd1) && (ret != 0xe1)) {
		printk("Version != d1 or e1\n");
		goto error;
	}

	/* create dvb_frontend */
969
	memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);

	return NULL;
}

static struct dvb_frontend_ops cx24123_ops = {

	.info = {
		.name = "Conexant CX24123/CX24109",
		.type = FE_QPSK,
		.frequency_min = 950000,
		.frequency_max = 2150000,
		.frequency_stepsize = 1011, /* kHz for QPSK frontends */
987
		.frequency_tolerance = 5000,
988 989 990 991
		.symbol_rate_min = 1000000,
		.symbol_rate_max = 45000000,
		.caps = FE_CAN_INVERSION_AUTO |
			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
992 993
			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
			FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
			FE_CAN_QPSK | FE_CAN_RECOVER
	},

	.release = cx24123_release,

	.init = cx24123_initfe,
	.set_frontend = cx24123_set_frontend,
	.get_frontend = cx24123_get_frontend,
	.read_status = cx24123_read_status,
	.read_ber = cx24123_read_ber,
	.read_signal_strength = cx24123_read_signal_strength,
	.read_snr = cx24123_read_snr,
	.read_ucblocks = cx24123_read_ucblocks,
	.diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1008
	.diseqc_send_burst = cx24123_diseqc_send_burst,
1009 1010 1011 1012 1013
	.set_tone = cx24123_set_tone,
	.set_voltage = cx24123_set_voltage,
};

module_param(debug, int, 0644);
1014
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1015

1016 1017 1018
module_param(force_band, int, 0644);
MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off).");

1019 1020 1021 1022 1023
MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(cx24123_attach);