1. 08 Nov, 2006 1 commit
    • Gary Hade's avatar
      [CPUFREQ] speedstep-centrino should ignore upper performance control bits · d7a1944e
      Gary Hade authored
      On some systems such as the IBM x3650 there are bits set in the
      upper half of the control values provided by the _PSS object.
      These bits are only relevant for cpufreq drivers that use IO ports
      which are not currently supported by the speedstep-centrino driver.
      The current MSR oriented code assumes that upper bits are not set
      and thus fails to work correctly when they are.  e.g. the control
      and status value equality check fails even though the ACPI spec
      allows the inequality.
      Signed-off-by: default avatarGary Hade <garyh@us.ibm.com>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      d7a1944e
  2. 07 Nov, 2006 2 commits
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  4. 18 Oct, 2006 4 commits
  5. 15 Oct, 2006 19 commits
  6. 14 Oct, 2006 11 commits