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  1. 30 Jun, 2008 1 commit
    • Ugo Riboni's avatar
      Fix kernel build failure with build-id-supporting binutils · 9523d091
      Ugo Riboni authored
      Patch from upstream, suggested by Koen Kooi <k.kooi@student.utwente.nl>
      Original description below.
      
      Newer versions of binutils support --build-id, which adds an ELF
      note section called ".note.gnu.build-id" to the output.  On the ARM
      kernel build, because there is no explicit mention of this section
      in the shipped ld script, this section is placed at vaddr 0x00000000
      (whereas the normal kernel text/data typically starts at vaddr
      0xc0008000), causing the output of objcopy (Image) to produce a 3G+
      file.
      
      This patch makes objcopy strip the .note.gnu.build-id section from
      the Image file along with all other note sections, which fixes the
      build.
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      9523d091
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  24. 28 Mar, 2006 2 commits
    • Lennert Buytenhek's avatar
      [ARM] 3388/1: ixp23xx: add core ixp23xx support · c4713074
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the Intel ixp23xx series of CPUs.  The
      ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
      interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
      MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
      Switch Fabric unit almost identical to the one on the ixp2400, two
      xscale (8250ish) UARTs and a bunch of other stuff.
      
      This patch adds the core ixp23xx support code, and support for the
      ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
      Espresso platforms.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c4713074
    • Lennert Buytenhek's avatar
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the new XScale v3 core.  This is an
      ARMv5 ISA core with the following additions:
      
      - L2 cache
      - I/O coherency support (on select chipsets)
      - Low-Locality Reference cache attributes (replaces mini-cache)
      - Supersections (v6 compatible)
      - 36-bit addressing (v6 compatible)
      - Single instruction cache line clean/invalidate
      - LRU cache replacement (vs round-robin)
      
      I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
      cores have separate errata and have to handle things like L2, so it
      is simpler to keep it separate.
      
      L2 cache support is currently a build option because the L2 enable
      bit must be set before we enable the MMU and there is no easy way to
      capture command line parameters at this point.
      
      There are still optimizations that can be done such as using LLR for
      copypage (in theory using the exisiting mini-cache code) but those
      can be addressed down the road.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a
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