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  1. 03 May, 2007 3 commits
    • Kenji Kaneshige's avatar
      pciehp: Event handling rework · 5d386e1a
      Kenji Kaneshige authored 
      The event handler of PCIEHP driver is unnecessarily very complex. In
addition, current event handler can only a fixed number of events at
the same time, and some of events would be lost if several number of
events happened at the same time.

This patch simplify the event handler using 'work queue', and it also
fix the above-mentioned issue.
Signed-off-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: default avatarKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      5d386e1a
    • Brian King's avatar
      pci: New PCI-E reset API · f7bdd12d
      Brian King authored 
      Adds a new API which can be used to issue various types
of PCI-E reset, including PCI-E warm reset and PCI-E hot reset.
This is needed for an ipr PCI-E adapter which does not properly
implement BIST. Running BIST on this adapter results in PCI-E
errors. The only reliable reset mechanism that exists on this
hardware is PCI Fundamental reset (warm reset). Since driving
this type of reset is architecture unique, this provides the
necessary hooks for architectures to add this support.
Signed-off-by: default avatarBrian King <brking@linux.vnet.ibm.com>
Acked-by: default avatarLinas Vepstas <linas@austin.ibm.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      f7bdd12d
    • Mitch Williams's avatar
      PCI: Flush MSI-X table writes · 988cbb15
      Mitch Williams authored 
      This patch fixes a kernel bug which is triggered when using the
irqbalance daemon with MSI-X hardware.

Because both MSI-X interrupt messages and MSI-X table writes are posted,
it's possible for them to cross while in-flight.  This results in
interrupts being received long after the kernel thinks they're disabled,
and in interrupts being sent to stale vectors after rebalancing.

This patch performs a read flush after writes to the MSI-X table for
mask and unmask operations.  Since the SMP affinity is set while
the interrupt is masked, and since it's unmasked immediately after,
no additional flushes are required in the various affinity setting
routines.

This patch has been validated with (unreleased) network hardware which
uses MSI-X.

Revised with input from Eric Biederman.
Signed-off-by: default avatarMitch Williams <mitch.a.williams@intel.com>
Acked-by: default avatar"Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      988cbb15
  3. 01 May, 2007 1 commit
    • Linus Torvalds's avatar
      libata: honour host controllers that want just one host · dc87c398
      Linus Torvalds authored 
      The Marvell IDE interface on my machine would hit a BUG_ON() in
lib/iomem.c because it was calling ata_pci_init_one() specifying just a
single port on the host, but that would actually end up trying to
initialize two ports, the second one with bogus information.

This fixes "ata_pci_init_one()" so that it actually passes down the
n_ports variable that it got from the low-level driver to the host
allocation routine ("ata_host_alloc_pinfo()"), which results in the ATA
layer actually having the correct port number information.

And in order to make it all work, I also needed to fix a few places that
had incorrectly hard-coded the fact that a host always had exactly two
ports (both ata_pci_init_bmdma() and ata_request_legacy_irqs() would
just always iterate over both ports).
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      dc87c398
  5. 30 Apr, 2007 36 commits