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  1. 11 Jul, 2007 1 commit
  2. 11 May, 2007 2 commits
  3. 09 May, 2007 1 commit
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  8. 11 Feb, 2007 1 commit
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  10. 07 Dec, 2006 2 commits
  11. 29 Oct, 2006 1 commit
  12. 27 Sep, 2006 5 commits
  13. 25 Sep, 2006 2 commits
  14. 28 Aug, 2006 1 commit
  15. 29 Jun, 2006 1 commit
  16. 19 Jun, 2006 1 commit
  17. 18 Jun, 2006 1 commit
  18. 09 Jun, 2006 1 commit
  19. 25 Apr, 2006 1 commit
  20. 04 Apr, 2006 1 commit
  21. 28 Mar, 2006 2 commits
    • Lennert Buytenhek's avatar
      [ARM] 3388/1: ixp23xx: add core ixp23xx support · c4713074
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the Intel ixp23xx series of CPUs.  The
      ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
      interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
      MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
      Switch Fabric unit almost identical to the one on the ixp2400, two
      xscale (8250ish) UARTs and a bunch of other stuff.
      
      This patch adds the core ixp23xx support code, and support for the
      ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
      Espresso platforms.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c4713074
    • Lennert Buytenhek's avatar
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      Lennert Buytenhek authored
      Patch from Lennert Buytenhek
      
      This patch adds support for the new XScale v3 core.  This is an
      ARMv5 ISA core with the following additions:
      
      - L2 cache
      - I/O coherency support (on select chipsets)
      - Low-Locality Reference cache attributes (replaces mini-cache)
      - Supersections (v6 compatible)
      - 36-bit addressing (v6 compatible)
      - Single instruction cache line clean/invalidate
      - LRU cache replacement (vs round-robin)
      
      I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
      cores have separate errata and have to handle things like L2, so it
      is simpler to keep it separate.
      
      L2 cache support is currently a build option because the L2 enable
      bit must be set before we enable the MMU and there is no easy way to
      capture command line parameters at this point.
      
      There are still optimizations that can be done such as using LLR for
      copypage (in theory using the exisiting mini-cache code) but those
      can be addressed down the road.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a
  22. 27 Mar, 2006 2 commits
  23. 21 Mar, 2006 1 commit
  24. 05 Mar, 2006 1 commit
  25. 14 Jan, 2006 1 commit
  26. 09 Jan, 2006 1 commit
  27. 08 Jan, 2006 1 commit
  28. 03 Jan, 2006 1 commit
  29. 10 Nov, 2005 1 commit
    • Tony Lindgren's avatar
      [ARM] 3145/1: OMAP 3a/5: Add support for omap24xx · 1dbae815
      Tony Lindgren authored
      Patch from Tony Lindgren
      
      This patch adds support for omap24xx series of processors.
      The files live in arch/arm/mach-omap2, and share common
      files with omap15xx and omap16xx processors in
      arch/arm/plat-omap.
      
      Omap24xx support was originally added for 2.6.9 by TI.
      This code was then improved and integrated to share common
      code with omap15xx and omap16xx processors by various
      omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak,
      Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah
      et al.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      1dbae815
  30. 04 Nov, 2005 1 commit
    • Nicolas Pitre's avatar
      [ARM] 3097/1: change library link ordering · 30c2f90b
      Nicolas Pitre authored
      Patch from Nicolas Pitre
      
      We have an optimized sha1 routine (arch/arm/lib/sha1.S) meant to
      override the generic one in lib/sha1.c.
      
      Unfortunately lib/lib.a is listed _before_ arch/arm/lib/lib.a in the
      link argument list and therefore the architecture specific lib functions
      are not picked up before the generic versions.
      
      This patch is a quick fix to change that ordering for ARM.  Here's what
      the kbuild maintainer had to say about it (was also CC'd on lkml):
      
      On Wed, 2 Nov 2005, Sam Ravnborg wrote:
      > This looks like an obvious way to achive correct ordering.
      > We could change it so arch defines always took precedence but
      > the above is so simple that it is not worth the effort.
      Signed-off-by: default avatarNicolas Pitre <nico@cam.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      30c2f90b