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linux-davinci-2.6.23
Commit f6bb6492 authored by Tony Lindgren's avatar Tony Lindgren
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ARM: OMAP: Update include files 

Sync with linux-omap tree. Updates from various OMAP developers.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 88d7bd8c
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Showing with 156 additions and 27 deletions
include/asm-arm/arch-omap/board-h2.h
View file @ f6bb6492
......@@ -34,11 +34,6 @@
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_START 0x04000300
/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
#define OMAP_NOR_FLASH_SIZE SZ_32M
#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
......
include/asm-arm/arch-omap/board-h3.h
View file @ f6bb6492
......@@ -30,11 +30,6 @@
/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
#define OMAP1710_ETHR_START 0x04000300
/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
#define OMAP_NOR_FLASH_SIZE SZ_32M
#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
......
include/asm-arm/arch-omap/board-osk.h
View file @ f6bb6492
......@@ -32,10 +32,5 @@
/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
#define OMAP_OSK_ETHR_START 0x04800300
/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000
#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M
#define OMAP_OSK_NOR_FLASH_START 0x00000000
#endif /* __ASM_ARCH_OMAP_OSK_H */
include/asm-arm/arch-omap/board.h
View file @ f6bb6492
......@@ -16,10 +16,11 @@
/* Different peripheral ids */
#define OMAP_TAG_CLOCK 0x4f01
#define OMAP_TAG_MMC 0x4f02
#define OMAP_TAG_UART 0x4f03
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
#define OMAP_TAG_USB 0x4f04
#define OMAP_TAG_LCD 0x4f05
#define OMAP_TAG_GPIO_SWITCH 0x4f06
#define OMAP_TAG_UART 0x4f07
#define OMAP_TAG_BOOT_REASON 0x4f80
#define OMAP_TAG_FLASH_PART 0x4f81
......@@ -35,7 +36,7 @@ struct omap_mmc_config {
s16 mmc1_switch_pin, mmc2_switch_pin;
};
struct omap_uart_config {
struct omap_serial_console_config {
u8 console_uart;
u32 console_speed;
};
......@@ -82,7 +83,8 @@ struct omap_lcd_config {
*/
#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
struct omap_gpio_switch_config {
char name[12];
u16 gpio;
......@@ -99,6 +101,10 @@ struct omap_boot_reason_config {
char reason_str[12];
};
struct omap_uart_config {
/* Bit field of UARTs present; bit 0 --> UART1 */
unsigned int enabled_uarts;
};
struct omap_board_config_entry {
u16 tag;
......
include/asm-arm/arch-omap/hardware.h
View file @ f6bb6492
......@@ -52,6 +52,19 @@
* ---------------------------------------------------------------------------
*/
/*
* ----------------------------------------------------------------------------
* Timers
* ----------------------------------------------------------------------------
*/
#define OMAP_MPU_TIMER1_BASE (0xfffec500)
#define OMAP_MPU_TIMER2_BASE (0xfffec600)
#define OMAP_MPU_TIMER3_BASE (0xfffec700)
#define MPU_TIMER_FREE (1 << 6)
#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
#define MPU_TIMER_AR (1 << 1)
#define MPU_TIMER_ST (1 << 0)
/*
* ----------------------------------------------------------------------------
* Clocks
......@@ -78,6 +91,7 @@
/* DSP clock control */
#define DSP_CONFIG_REG_BASE (0xe1008000)
#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
......@@ -88,6 +102,7 @@
*/
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
......@@ -268,17 +283,10 @@
* Processor specific defines
* ---------------------------------------------------------------------------
*/
#ifdef CONFIG_ARCH_OMAP730
#include "omap730.h"
#endif
#ifdef CONFIG_ARCH_OMAP1510
#include "omap730.h"
#include "omap1510.h"
#endif
#ifdef CONFIG_ARCH_OMAP16XX
#include "omap16xx.h"
#endif
/*
* ---------------------------------------------------------------------------
......
include/asm-arm/arch-omap/irqs.h
View file @ f6bb6492
......@@ -159,6 +159,7 @@
#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
#define INT_1610_MMC2 (42 + IH2_BASE)
#define INT_1610_CF (43 + IH2_BASE)
#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
#define INT_1610_SPI (49 + IH2_BASE)
#define INT_1610_DMA_CH6 (53 + IH2_BASE)
......@@ -238,6 +239,8 @@
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
#ifndef __ASSEMBLY__
extern void omap_init_irq(void);
#endif
......
include/asm-arm/arch-omap/omap16xx.h
View file @ f6bb6492
......@@ -183,5 +183,37 @@
#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
/*
* ---------------------------------------------------------------------------
* Watchdog timer
* ---------------------------------------------------------------------------
*/
/* 32-bit Watchdog timer in OMAP 16XX */
#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
#define WCLR_PRE_SHIFT 5
#define WCLR_PTV_SHIFT 2
#define WWPS_W_PEND_WSPR (1 << 4)
#define WWPS_W_PEND_WTGR (1 << 3)
#define WWPS_W_PEND_WLDR (1 << 2)
#define WWPS_W_PEND_WCRR (1 << 1)
#define WWPS_W_PEND_WCLR (1 << 0)
#define WSPR_ENABLE_0 (0x0000bbbb)
#define WSPR_ENABLE_1 (0x00004444)
#define WSPR_DISABLE_0 (0x0000aaaa)
#define WSPR_DISABLE_1 (0x00005555)
#endif /* __ASM_ARCH_OMAP16XX_H */
include/asm-arm/arch-omap/system.h
View file @ f6bb6492
......@@ -5,7 +5,9 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/config.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/mach-types.h>
static inline void arch_idle(void)
{
......@@ -14,7 +16,24 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
omap_writew(1, ARM_RSTCT1);
#ifdef CONFIG_ARCH_OMAP16XX
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
#endif
#ifdef CONFIG_MACH_VOICEBLUE
if (machine_is_voiceblue())
voiceblue_reset();
else
#endif
omap_writew(1, ARM_RSTCT1);
}
#endif
include/asm-arm/arch-omap/tps65010.h
View file @ f6bb6492
......@@ -28,6 +28,66 @@
#ifndef __ASM_ARCH_TPS65010_H
#define __ASM_ARCH_TPS65010_H
/*
* ----------------------------------------------------------------------------
* Registers, all 8 bits
* ----------------------------------------------------------------------------
*/
#define TPS_CHGSTATUS 0x01
# define TPS_CHG_USB (1 << 7)
# define TPS_CHG_AC (1 << 6)
# define TPS_CHG_THERM (1 << 5)
# define TPS_CHG_TERM (1 << 4)
# define TPS_CHG_TAPER_TMO (1 << 3)
# define TPS_CHG_CHG_TMO (1 << 2)
# define TPS_CHG_PRECHG_TMO (1 << 1)
# define TPS_CHG_TEMP_ERR (1 << 0)
#define TPS_REGSTATUS 0x02
# define TPS_REG_ONOFF (1 << 7)
# define TPS_REG_COVER (1 << 6)
# define TPS_REG_UVLO (1 << 5)
# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */
# define TPS_REG_PG_LD02 (1 << 3)
# define TPS_REG_PG_LD01 (1 << 2)
# define TPS_REG_PG_MAIN (1 << 1)
# define TPS_REG_PG_CORE (1 << 0)
#define TPS_MASK1 0x03
#define TPS_MASK2 0x04
#define TPS_ACKINT1 0x05
#define TPS_ACKINT2 0x06
#define TPS_CHGCONFIG 0x07
# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */
# define TPS65013_AUA (1 << 7) /* 65011/65013 */
# define TPS_CHARGE_RESET (1 << 6)
# define TPS_CHARGE_FAST (1 << 5)
# define TPS_CHARGE_CURRENT (3 << 3)
# define TPS_VBUS_500MA (1 << 2)
# define TPS_VBUS_CHARGING (1 << 1)
# define TPS_CHARGE_ENABLE (1 << 0)
#define TPS_LED1_ON 0x08
#define TPS_LED1_PER 0x09
#define TPS_LED2_ON 0x0a
#define TPS_LED2_PER 0x0b
#define TPS_VDCDC1 0x0c
# define TPS_ENABLE_LP (1 << 3)
#define TPS_VDCDC2 0x0d
#define TPS_VREGS1 0x0e
# define TPS_LDO2_ENABLE (1 << 7)
# define TPS_LDO2_OFF (1 << 6)
# define TPS_VLDO2_3_0V (3 << 4)
# define TPS_VLDO2_2_75V (2 << 4)
# define TPS_VLDO2_2_5V (1 << 4)
# define TPS_VLDO2_1_8V (0 << 4)
# define TPS_LDO1_ENABLE (1 << 3)
# define TPS_LDO1_OFF (1 << 2)
# define TPS_VLDO1_3_0V (3 << 0)
# define TPS_VLDO1_2_75V (2 << 0)
# define TPS_VLDO1_2_5V (1 << 0)
# define TPS_VLDO1_ADJ (0 << 0)
#define TPS_MASK3 0x0f
#define TPS_DEFGPIO 0x10
/*
* ----------------------------------------------------------------------------
* Macros used by exported functions
......@@ -71,10 +131,26 @@ extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
*/
extern int tps65010_set_led(unsigned led, unsigned mode);
/* tps65010_set_vib parameter:
* value: ON or OFF
*/
extern int tps65010_set_vib(unsigned value);
/* tps65010_set_low_pwr parameter:
* mode: ON or OFF
*/
extern int tps65010_set_low_pwr(unsigned mode);
/* tps65010_config_vregs1 parameter:
* value to be written to VREGS1 register
* Note: The complete register is written, set all bits you need
*/
extern int tps65010_config_vregs1(unsigned value);
/* tps65013_set_low_pwr parameter:
* mode: ON or OFF
*/
extern int tps65013_set_low_pwr(unsigned mode);
#endif /* __ASM_ARCH_TPS65010_H */
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