Commit f264cc28 authored by Olof Johansson's avatar Olof Johansson Committed by Linus Torvalds

[PATCH] ppc64: add 970MP PVR

Add PVR value and tests for 970MP.  Also switch to a simpler (but slightly
longer) check at init time for simplicity.
Signed-off-by: default avatarOlof Johansson <olof@austin.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: default avatarPaul Mackerras <paulus@samba.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 96e28449
...@@ -31,10 +31,13 @@ _GLOBAL(__970_cpu_preinit) ...@@ -31,10 +31,13 @@ _GLOBAL(__970_cpu_preinit)
*/ */
mfspr r0,SPRN_PVR mfspr r0,SPRN_PVR
srwi r0,r0,16 srwi r0,r0,16
cmpwi cr0,r0,0x39 cmpwi r0,0x39
cmpwi cr1,r0,0x3c beq 1f
cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cmpwi r0,0x3c
beq 1f
cmpwi r0,0x44
bnelr bnelr
1:
/* Make sure HID4:rm_ci is off before MMU is turned off, that large /* Make sure HID4:rm_ci is off before MMU is turned off, that large
* pages are enabled with HID4:61 and clear HID5:DCBZ_size and * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
...@@ -133,12 +136,14 @@ _GLOBAL(__save_cpu_setup) ...@@ -133,12 +136,14 @@ _GLOBAL(__save_cpu_setup)
/* We only deal with 970 for now */ /* We only deal with 970 for now */
mfspr r0,SPRN_PVR mfspr r0,SPRN_PVR
srwi r0,r0,16 srwi r0,r0,16
cmpwi cr0,r0,0x39 cmpwi r0,0x39
cmpwi cr1,r0,0x3c beq 1f
cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cmpwi r0,0x3c
bne 1f beq 1f
cmpwi r0,0x44
/* Save HID0,1,4 and 5 */ bne 2f
1: /* Save HID0,1,4 and 5 */
mfspr r3,SPRN_HID0 mfspr r3,SPRN_HID0
std r3,CS_HID0(r5) std r3,CS_HID0(r5)
mfspr r3,SPRN_HID1 mfspr r3,SPRN_HID1
...@@ -148,7 +153,7 @@ _GLOBAL(__save_cpu_setup) ...@@ -148,7 +153,7 @@ _GLOBAL(__save_cpu_setup)
mfspr r3,SPRN_HID5 mfspr r3,SPRN_HID5
std r3,CS_HID5(r5) std r3,CS_HID5(r5)
1: 2:
mtcr r7 mtcr r7
blr blr
...@@ -165,12 +170,14 @@ _GLOBAL(__restore_cpu_setup) ...@@ -165,12 +170,14 @@ _GLOBAL(__restore_cpu_setup)
/* We only deal with 970 for now */ /* We only deal with 970 for now */
mfspr r0,SPRN_PVR mfspr r0,SPRN_PVR
srwi r0,r0,16 srwi r0,r0,16
cmpwi cr0,r0,0x39 cmpwi r0,0x39
cmpwi cr1,r0,0x3c beq 1f
cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cmpwi r0,0x3c
bne 1f beq 1f
cmpwi r0,0x44
bnelr
/* Before accessing memory, we make sure rm_ci is clear */ 1: /* Before accessing memory, we make sure rm_ci is clear */
li r0,0 li r0,0
mfspr r3,SPRN_HID4 mfspr r3,SPRN_HID4
rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
...@@ -223,6 +230,5 @@ _GLOBAL(__restore_cpu_setup) ...@@ -223,6 +230,5 @@ _GLOBAL(__restore_cpu_setup)
mtspr SPRN_HID5,r3 mtspr SPRN_HID5,r3
sync sync
isync isync
1:
blr blr
...@@ -183,6 +183,21 @@ struct cpu_spec cpu_specs[] = { ...@@ -183,6 +183,21 @@ struct cpu_spec cpu_specs[] = {
.cpu_setup = __setup_cpu_ppc970, .cpu_setup = __setup_cpu_ppc970,
.firmware_features = COMMON_PPC64_FW, .firmware_features = COMMON_PPC64_FW,
}, },
{ /* PPC970MP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00440000,
.cpu_name = "PPC970MP",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_ppc970,
.firmware_features = COMMON_PPC64_FW,
},
{ /* Power5 */ { /* Power5 */
.pvr_mask = 0xffff0000, .pvr_mask = 0xffff0000,
.pvr_value = 0x003a0000, .pvr_value = 0x003a0000,
......
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