omap2 clock: fix clksel divisor bug

For clksel clocks, omap2_clk_set_rate() incorrectly divides the parent
clock's rate by the actual bits of the register field, rather than the
translated divisor value.  This happens to work for most clksel
clocks, since the register bit fields are equal to the divisor values.
But for some clocks, such as sys_clkout, the code gets the resulting
rate wrong.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/clock.c

@@ -819,7 +819,7 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 		reg_val |= (field_val << div_off);
 		cm_write_reg(reg_val, reg);
 		wmb();
-		clk->rate = clk->parent->rate / field_val;
+		clk->rate = clk->parent->rate / new_div;
 
 		if (clk->flags & DELAYED_APP) {
 			prm_write_reg(OMAP24XX_VALID_CONFIG,