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linux
linux-davinci-2.6.23
Commits
c04d66bb
Commit
c04d66bb
authored
Jul 12, 2007
by
Bryan Wu
Browse files
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Plain Diff
Blackfin arch: clean up some coding style issues
Signed-off-by:
Bryan Wu
<
bryan.wu@analog.com
>
parent
1d189474
Changes
5
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5 changed files
with
8 additions
and
13 deletions
+8
-13
arch/blackfin/mach-common/ints-priority-dc.c
arch/blackfin/mach-common/ints-priority-dc.c
+2
-2
arch/blackfin/mach-common/ints-priority-sc.c
arch/blackfin/mach-common/ints-priority-sc.c
+6
-7
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+0
-1
include/asm-blackfin/mach-bf561/cdefBF561.h
include/asm-blackfin/mach-bf561/cdefBF561.h
+0
-1
include/asm-blackfin/mman.h
include/asm-blackfin/mman.h
+0
-2
No files found.
arch/blackfin/mach-common/ints-priority-dc.c
View file @
c04d66bb
...
@@ -371,8 +371,8 @@ int __init init_arch_irq(void)
...
@@ -371,8 +371,8 @@ int __init init_arch_irq(void)
bfin_write_SICA_IMASK1
(
SIC_UNMASK_ALL
);
bfin_write_SICA_IMASK1
(
SIC_UNMASK_ALL
);
SSYNC
();
SSYNC
();
bfin_write_SICA_IWR0
(
IWR_ENABLE_ALL
);
bfin_write_SICA_IWR0
(
IWR_ENABLE_ALL
);
bfin_write_SICA_IWR1
(
IWR_ENABLE_ALL
);
bfin_write_SICA_IWR1
(
IWR_ENABLE_ALL
);
local_irq_disable
();
local_irq_disable
();
...
...
arch/blackfin/mach-common/ints-priority-sc.c
View file @
c04d66bb
...
@@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq)
...
@@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq)
unsigned
mask_bank
,
mask_bit
;
unsigned
mask_bank
,
mask_bit
;
mask_bank
=
(
irq
-
(
IRQ_CORETMR
+
1
))
/
32
;
mask_bank
=
(
irq
-
(
IRQ_CORETMR
+
1
))
/
32
;
mask_bit
=
(
irq
-
(
IRQ_CORETMR
+
1
))
%
32
;
mask_bit
=
(
irq
-
(
IRQ_CORETMR
+
1
))
%
32
;
bfin_write_SIC_IMASK
(
mask_bank
,
bfin_read_SIC_IMASK
(
mask_bank
)
&
\
bfin_write_SIC_IMASK
(
mask_bank
,
bfin_read_SIC_IMASK
(
mask_bank
)
&
~
(
1
<<
mask_bit
));
~
(
1
<<
mask_bit
));
#endif
#endif
SSYNC
();
SSYNC
();
}
}
...
@@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq)
...
@@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq)
#else
#else
unsigned
mask_bank
,
mask_bit
;
unsigned
mask_bank
,
mask_bit
;
mask_bank
=
(
irq
-
(
IRQ_CORETMR
+
1
))
/
32
;
mask_bank
=
(
irq
-
(
IRQ_CORETMR
+
1
))
/
32
;
mask_bit
=
(
irq
-
(
IRQ_CORETMR
+
1
))
%
32
;
mask_bit
=
(
irq
-
(
IRQ_CORETMR
+
1
))
%
32
;
bfin_write_SIC_IMASK
(
mask_bank
,
bfin_read_SIC_IMASK
(
mask_bank
)
|
\
bfin_write_SIC_IMASK
(
mask_bank
,
bfin_read_SIC_IMASK
(
mask_bank
)
|
(
1
<<
mask_bit
));
(
1
<<
mask_bit
));
#endif
#endif
SSYNC
();
SSYNC
();
}
}
...
@@ -728,7 +728,7 @@ int __init init_arch_irq(void)
...
@@ -728,7 +728,7 @@ int __init init_arch_irq(void)
bfin_write_SIC_IMASK2
(
SIC_UNMASK_ALL
);
bfin_write_SIC_IMASK2
(
SIC_UNMASK_ALL
);
bfin_write_SIC_IWR0
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR0
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR1
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR1
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR2
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR2
(
IWR_ENABLE_ALL
);
#else
#else
bfin_write_SIC_IMASK
(
SIC_UNMASK_ALL
);
bfin_write_SIC_IMASK
(
SIC_UNMASK_ALL
);
bfin_write_SIC_IWR
(
IWR_ENABLE_ALL
);
bfin_write_SIC_IWR
(
IWR_ENABLE_ALL
);
...
@@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp)
...
@@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp)
sic_status
[
0
]
=
bfin_read_SIC_ISR
(
0
)
&
bfin_read_SIC_IMASK
(
0
);
sic_status
[
0
]
=
bfin_read_SIC_ISR
(
0
)
&
bfin_read_SIC_IMASK
(
0
);
sic_status
[
1
]
=
bfin_read_SIC_ISR
(
1
)
&
bfin_read_SIC_IMASK
(
1
);
sic_status
[
1
]
=
bfin_read_SIC_ISR
(
1
)
&
bfin_read_SIC_IMASK
(
1
);
sic_status
[
2
]
=
bfin_read_SIC_ISR
(
2
)
&
bfin_read_SIC_IMASK
(
2
);
sic_status
[
2
]
=
bfin_read_SIC_ISR
(
2
)
&
bfin_read_SIC_IMASK
(
2
);
for
(;;
ivg
++
)
{
for
(;;
ivg
++
)
{
if
(
ivg
>=
ivg_stop
)
{
if
(
ivg
>=
ivg_stop
)
{
...
...
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
View file @
c04d66bb
...
@@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
...
@@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32
(
SIC_IWR0
,
iwr0
);
bfin_write32
(
SIC_IWR0
,
iwr0
);
bfin_write32
(
SIC_IWR1
,
iwr1
);
bfin_write32
(
SIC_IWR1
,
iwr1
);
bfin_write32
(
SIC_IWR2
,
iwr2
);
bfin_write32
(
SIC_IWR2
,
iwr2
);
}
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
...
...
include/asm-blackfin/mach-bf561/cdefBF561.h
View file @
c04d66bb
...
@@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
...
@@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
local_irq_restore
(
flags
);
local_irq_restore
(
flags
);
bfin_write32
(
SICA_IWR0
,
iwr0
);
bfin_write32
(
SICA_IWR0
,
iwr0
);
bfin_write32
(
SICA_IWR1
,
iwr1
);
bfin_write32
(
SICA_IWR1
,
iwr1
);
}
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
...
...
include/asm-blackfin/mman.h
View file @
c04d66bb
...
@@ -22,8 +22,6 @@
...
@@ -22,8 +22,6 @@
#define MAP_NORESERVE 0x4000
/* don't check for reservations */
#define MAP_NORESERVE 0x4000
/* don't check for reservations */
#define MAP_POPULATE 0x8000
/* populate (prefault) pagetables */
#define MAP_POPULATE 0x8000
/* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000
/* do not block on IO */
#define MAP_NONBLOCK 0x10000
/* do not block on IO */
#define MAP_UNINITIALIZE 0x4000000
/* For anonymous mmap, memory could
be uninitialized. */
#define MS_ASYNC 1
/* sync memory asynchronously */
#define MS_ASYNC 1
/* sync memory asynchronously */
#define MS_INVALIDATE 2
/* invalidate the caches */
#define MS_INVALIDATE 2
/* invalidate the caches */
...
...
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