Commit c03af5bf authored by Syed Mohammed, Khasim's avatar Syed Mohammed, Khasim Committed by Tony Lindgren

FIX BUG in GPT1 Clock Selection

The GPT1 CLK SEL register was getting wrong src register, due to which GPT1 was not able to select SYS_CLK as input.
Signed-off-by: default avatarSyed Mohammed Khasim <x0khasim@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent e7121825
...@@ -1489,7 +1489,7 @@ static struct clk gpt1_fck = { ...@@ -1489,7 +1489,7 @@ static struct clk gpt1_fck = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT, .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
.clksel = omap24xx_gpt_clksel, .clksel = omap24xx_gpt_clksel,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
......
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