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linux-davinci-2.6.23
Commit a9c4814d authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King
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[ARM] 3151/1: make various assembly local labels actually local (io-*.S) 

Patch from Nicolas Pitre

For assembly labels to actually be local they must start with ".L" and
not only "." otherwise they still remain visible in the final link and
clutter kallsyms needlessly, and possibly make for unclear symbolic
backtrace. This patch simply inserts a"L" where appropriate. The code
itself is unchanged.
Signed-off-by: default avatarNicolas Pitre <nico@cam.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 7ba11a9c
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Showing with 82 additions and 80 deletions
arch/arm/lib/io-acorn.S
View file @ a9c4814d
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
.text .text
.align .align
.iosl_warning: .Liosl_warning:
.ascii "<4>insl/outsl not implemented, called from %08lX\0" .ascii "<4>insl/outsl not implemented, called from %08lX\0"
.align .align
...@@ -27,6 +27,6 @@ ...@@ -27,6 +27,6 @@
*/ */
ENTRY(insl) ENTRY(insl)
ENTRY(outsl) ENTRY(outsl)
adr r0, .iosl_warning adr r0, .Liosl_warning
mov r1, lr mov r1, lr
b printk b printk
arch/arm/lib/io-readsb.S
View file @ a9c4814d
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/assembler.h> #include <asm/assembler.h>
.insb_align: rsb ip, ip, #4 .Linsb_align: rsb ip, ip, #4
cmp ip, r2 cmp ip, r2
movgt ip, r2 movgt ip, r2
cmp ip, #2 cmp ip, #2
...@@ -21,20 +21,20 @@ ...@@ -21,20 +21,20 @@
ldrgtb r3, [r0] ldrgtb r3, [r0]
strgtb r3, [r1], #1 strgtb r3, [r1], #1
subs r2, r2, ip subs r2, r2, ip
bne .insb_aligned bne .Linsb_aligned
ENTRY(__raw_readsb) ENTRY(__raw_readsb)
teq r2, #0 @ do we have to check for the zero len? teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr moveq pc, lr
ands ip, r1, #3 ands ip, r1, #3
bne .insb_align bne .Linsb_align
.insb_aligned: stmfd sp!, {r4 - r6, lr} .Linsb_aligned: stmfd sp!, {r4 - r6, lr}
subs r2, r2, #16 subs r2, r2, #16
bmi .insb_no_16 bmi .Linsb_no_16
.insb_16_lp: ldrb r3, [r0] .Linsb_16_lp: ldrb r3, [r0]
ldrb r4, [r0] ldrb r4, [r0]
ldrb r5, [r0] ldrb r5, [r0]
mov r3, r3, put_byte_0 mov r3, r3, put_byte_0
...@@ -69,13 +69,13 @@ ENTRY(__raw_readsb) ...@@ -69,13 +69,13 @@ ENTRY(__raw_readsb)
stmia r1!, {r3 - r6} stmia r1!, {r3 - r6}
subs r2, r2, #16 subs r2, r2, #16
bpl .insb_16_lp bpl .Linsb_16_lp
tst r2, #15 tst r2, #15
LOADREGS(eqfd, sp!, {r4 - r6, pc}) LOADREGS(eqfd, sp!, {r4 - r6, pc})
.insb_no_16: tst r2, #8 .Linsb_no_16: tst r2, #8
beq .insb_no_8 beq .Linsb_no_8
ldrb r3, [r0] ldrb r3, [r0]
ldrb r4, [r0] ldrb r4, [r0]
...@@ -95,8 +95,8 @@ ENTRY(__raw_readsb) ...@@ -95,8 +95,8 @@ ENTRY(__raw_readsb)
orr r4, r4, ip, put_byte_3 orr r4, r4, ip, put_byte_3
stmia r1!, {r3, r4} stmia r1!, {r3, r4}
.insb_no_8: tst r2, #4 .Linsb_no_8: tst r2, #4
beq .insb_no_4 beq .Linsb_no_4
ldrb r3, [r0] ldrb r3, [r0]
ldrb r4, [r0] ldrb r4, [r0]
...@@ -108,7 +108,7 @@ ENTRY(__raw_readsb) ...@@ -108,7 +108,7 @@ ENTRY(__raw_readsb)
orr r3, r3, r6, put_byte_3 orr r3, r3, r6, put_byte_3
str r3, [r1], #4 str r3, [r1], #4
.insb_no_4: ands r2, r2, #3 .Linsb_no_4: ands r2, r2, #3
LOADREGS(eqfd, sp!, {r4 - r6, pc}) LOADREGS(eqfd, sp!, {r4 - r6, pc})
cmp r2, #2 cmp r2, #2
......
arch/arm/lib/io-readsw-armv3.S
View file @ a9c4814d
...@@ -11,16 +11,16 @@ ...@@ -11,16 +11,16 @@
#include <asm/assembler.h> #include <asm/assembler.h>
#include <asm/hardware.h> #include <asm/hardware.h>
.insw_bad_alignment: .Linsw_bad_alignment:
adr r0, .insw_bad_align_msg adr r0, .Linsw_bad_align_msg
mov r2, lr mov r2, lr
b panic b panic
.insw_bad_align_msg: .Linsw_bad_align_msg:
.asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
.align .align
.insw_align: tst r1, #1 .Linsw_align: tst r1, #1
bne .insw_bad_alignment bne .Linsw_bad_alignment
ldr r3, [r0] ldr r3, [r0]
strb r3, [r1], #1 strb r3, [r1], #1
...@@ -34,16 +34,16 @@ ENTRY(__raw_readsw) ...@@ -34,16 +34,16 @@ ENTRY(__raw_readsw)
teq r2, #0 @ do we have to check for the zero len? teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr moveq pc, lr
tst r1, #3 tst r1, #3
bne .insw_align bne .Linsw_align
.insw_aligned: mov ip, #0xff .Linsw_aligned: mov ip, #0xff
orr ip, ip, ip, lsl #8 orr ip, ip, ip, lsl #8
stmfd sp!, {r4, r5, r6, lr} stmfd sp!, {r4, r5, r6, lr}
subs r2, r2, #8 subs r2, r2, #8
bmi .no_insw_8 bmi .Lno_insw_8
.insw_8_lp: ldr r3, [r0] .Linsw_8_lp: ldr r3, [r0]
and r3, r3, ip and r3, r3, ip
ldr r4, [r0] ldr r4, [r0]
orr r3, r3, r4, lsl #16 orr r3, r3, r4, lsl #16
...@@ -66,13 +66,13 @@ ENTRY(__raw_readsw) ...@@ -66,13 +66,13 @@ ENTRY(__raw_readsw)
stmia r1!, {r3 - r6} stmia r1!, {r3 - r6}
subs r2, r2, #8 subs r2, r2, #8
bpl .insw_8_lp bpl .Linsw_8_lp
tst r2, #7 tst r2, #7
LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
.no_insw_8: tst r2, #4 .Lno_insw_8: tst r2, #4
beq .no_insw_4 beq .Lno_insw_4
ldr r3, [r0] ldr r3, [r0]
and r3, r3, ip and r3, r3, ip
...@@ -86,8 +86,8 @@ ENTRY(__raw_readsw) ...@@ -86,8 +86,8 @@ ENTRY(__raw_readsw)
stmia r1!, {r3, r4} stmia r1!, {r3, r4}
.no_insw_4: tst r2, #2 .Lno_insw_4: tst r2, #2
beq .no_insw_2 beq .Lno_insw_2
ldr r3, [r0] ldr r3, [r0]
and r3, r3, ip and r3, r3, ip
...@@ -96,7 +96,7 @@ ENTRY(__raw_readsw) ...@@ -96,7 +96,7 @@ ENTRY(__raw_readsw)
str r3, [r1], #4 str r3, [r1], #4
.no_insw_2: tst r2, #1 .Lno_insw_2: tst r2, #1
ldrne r3, [r0] ldrne r3, [r0]
strneb r3, [r1], #1 strneb r3, [r1], #1
movne r3, r3, lsr #8 movne r3, r3, lsr #8
......
arch/arm/lib/io-readsw-armv4.S
View file @ a9c4814d
...@@ -18,8 +18,8 @@ ...@@ -18,8 +18,8 @@
#endif #endif
.endm .endm
.insw_align: movs ip, r1, lsl #31 .Linsw_align: movs ip, r1, lsl #31
bne .insw_noalign bne .Linsw_noalign
ldrh ip, [r0] ldrh ip, [r0]
sub r2, r2, #1 sub r2, r2, #1
strh ip, [r1], #2 strh ip, [r1], #2
...@@ -28,14 +28,14 @@ ENTRY(__raw_readsw) ...@@ -28,14 +28,14 @@ ENTRY(__raw_readsw)
teq r2, #0 teq r2, #0
moveq pc, lr moveq pc, lr
tst r1, #3 tst r1, #3
bne .insw_align bne .Linsw_align
stmfd sp!, {r4, r5, lr} stmfd sp!, {r4, r5, lr}
subs r2, r2, #8 subs r2, r2, #8
bmi .no_insw_8 bmi .Lno_insw_8
.insw_8_lp: ldrh r3, [r0] .Linsw_8_lp: ldrh r3, [r0]
ldrh r4, [r0] ldrh r4, [r0]
pack r3, r3, r4 pack r3, r3, r4
...@@ -53,10 +53,10 @@ ENTRY(__raw_readsw) ...@@ -53,10 +53,10 @@ ENTRY(__raw_readsw)
subs r2, r2, #8 subs r2, r2, #8
stmia r1!, {r3 - r5, ip} stmia r1!, {r3 - r5, ip}
bpl .insw_8_lp bpl .Linsw_8_lp
.no_insw_8: tst r2, #4 .Lno_insw_8: tst r2, #4
beq .no_insw_4 beq .Lno_insw_4
ldrh r3, [r0] ldrh r3, [r0]
ldrh r4, [r0] ldrh r4, [r0]
...@@ -68,15 +68,15 @@ ENTRY(__raw_readsw) ...@@ -68,15 +68,15 @@ ENTRY(__raw_readsw)
stmia r1!, {r3, r4} stmia r1!, {r3, r4}
.no_insw_4: movs r2, r2, lsl #31 .Lno_insw_4: movs r2, r2, lsl #31
bcc .no_insw_2 bcc .Lno_insw_2
ldrh r3, [r0] ldrh r3, [r0]
ldrh ip, [r0] ldrh ip, [r0]
pack r3, r3, ip pack r3, r3, ip
str r3, [r1], #4 str r3, [r1], #4
.no_insw_2: ldrneh r3, [r0] .Lno_insw_2: ldrneh r3, [r0]
strneh r3, [r1] strneh r3, [r1]
ldmfd sp!, {r4, r5, pc} ldmfd sp!, {r4, r5, pc}
...@@ -93,7 +93,7 @@ ENTRY(__raw_readsw) ...@@ -93,7 +93,7 @@ ENTRY(__raw_readsw)
#define pull_hbyte1 lsr #8 #define pull_hbyte1 lsr #8
#endif #endif
.insw_noalign: stmfd sp!, {r4, lr} .Linsw_noalign: stmfd sp!, {r4, lr}
ldrccb ip, [r1, #-1]! ldrccb ip, [r1, #-1]!
bcc 1f bcc 1f
......
arch/arm/lib/io-writesb.S
View file @ a9c4814d
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#endif #endif
.endm .endm
.outsb_align: rsb ip, ip, #4 .Loutsb_align: rsb ip, ip, #4
cmp ip, r2 cmp ip, r2
movgt ip, r2 movgt ip, r2
cmp ip, #2 cmp ip, #2
...@@ -41,44 +41,45 @@ ...@@ -41,44 +41,45 @@
ldrgtb r3, [r1], #1 ldrgtb r3, [r1], #1
strgtb r3, [r0] strgtb r3, [r0]
subs r2, r2, ip subs r2, r2, ip
bne .outsb_aligned bne .Loutsb_aligned
ENTRY(__raw_writesb) ENTRY(__raw_writesb)
teq r2, #0 @ do we have to check for the zero len? teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr moveq pc, lr
ands ip, r1, #3 ands ip, r1, #3
bne .outsb_align bne .Loutsb_align
.outsb_aligned: stmfd sp!, {r4, r5, lr} .Loutsb_aligned:
stmfd sp!, {r4, r5, lr}
subs r2, r2, #16 subs r2, r2, #16
bmi .outsb_no_16 bmi .Loutsb_no_16
.outsb_16_lp: ldmia r1!, {r3, r4, r5, ip} .Loutsb_16_lp: ldmia r1!, {r3, r4, r5, ip}
outword r3 outword r3
outword r4 outword r4
outword r5 outword r5
outword ip outword ip
subs r2, r2, #16 subs r2, r2, #16
bpl .outsb_16_lp bpl .Loutsb_16_lp
tst r2, #15 tst r2, #15
LOADREGS(eqfd, sp!, {r4, r5, pc}) LOADREGS(eqfd, sp!, {r4, r5, pc})
.outsb_no_16: tst r2, #8 .Loutsb_no_16: tst r2, #8
beq .outsb_no_8 beq .Loutsb_no_8
ldmia r1!, {r3, r4} ldmia r1!, {r3, r4}
outword r3 outword r3
outword r4 outword r4
.outsb_no_8: tst r2, #4 .Loutsb_no_8: tst r2, #4
beq .outsb_no_4 beq .Loutsb_no_4
ldr r3, [r1], #4 ldr r3, [r1], #4
outword r3 outword r3
.outsb_no_4: ands r2, r2, #3 .Loutsb_no_4: ands r2, r2, #3
LOADREGS(eqfd, sp!, {r4, r5, pc}) LOADREGS(eqfd, sp!, {r4, r5, pc})
cmp r2, #2 cmp r2, #2
......
arch/arm/lib/io-writesw-armv3.S
View file @ a9c4814d
...@@ -11,16 +11,16 @@ ...@@ -11,16 +11,16 @@
#include <asm/assembler.h> #include <asm/assembler.h>
#include <asm/hardware.h> #include <asm/hardware.h>
.outsw_bad_alignment: .Loutsw_bad_alignment:
adr r0, .outsw_bad_align_msg adr r0, .Loutsw_bad_align_msg
mov r2, lr mov r2, lr
b panic b panic
.outsw_bad_align_msg: .Loutsw_bad_align_msg:
.asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
.align .align
.outsw_align: tst r1, #1 .Loutsw_align: tst r1, #1
bne .outsw_bad_alignment bne .Loutsw_bad_alignment
add r1, r1, #2 add r1, r1, #2
...@@ -35,14 +35,14 @@ ENTRY(__raw_writesw) ...@@ -35,14 +35,14 @@ ENTRY(__raw_writesw)
teq r2, #0 @ do we have to check for the zero len? teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr moveq pc, lr
tst r1, #3 tst r1, #3
bne .outsw_align bne .Loutsw_align
.outsw_aligned: stmfd sp!, {r4, r5, r6, lr} stmfd sp!, {r4, r5, r6, lr}
subs r2, r2, #8 subs r2, r2, #8
bmi .no_outsw_8 bmi .Lno_outsw_8
.outsw_8_lp: ldmia r1!, {r3, r4, r5, r6} .Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
mov ip, r3, lsl #16 mov ip, r3, lsl #16
orr ip, ip, ip, lsr #16 orr ip, ip, ip, lsr #16
...@@ -77,13 +77,13 @@ ENTRY(__raw_writesw) ...@@ -77,13 +77,13 @@ ENTRY(__raw_writesw)
str ip, [r0] str ip, [r0]
subs r2, r2, #8 subs r2, r2, #8
bpl .outsw_8_lp bpl .Loutsw_8_lp
tst r2, #7 tst r2, #7
LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
.no_outsw_8: tst r2, #4 .Lno_outsw_8: tst r2, #4
beq .no_outsw_4 beq .Lno_outsw_4
ldmia r1!, {r3, r4} ldmia r1!, {r3, r4}
...@@ -103,8 +103,8 @@ ENTRY(__raw_writesw) ...@@ -103,8 +103,8 @@ ENTRY(__raw_writesw)
orr ip, ip, ip, lsl #16 orr ip, ip, ip, lsl #16
str ip, [r0] str ip, [r0]
.no_outsw_4: tst r2, #2 .Lno_outsw_4: tst r2, #2
beq .no_outsw_2 beq .Lno_outsw_2
ldr r3, [r1], #4 ldr r3, [r1], #4
...@@ -116,7 +116,7 @@ ENTRY(__raw_writesw) ...@@ -116,7 +116,7 @@ ENTRY(__raw_writesw)
orr ip, ip, ip, lsl #16 orr ip, ip, ip, lsl #16
str ip, [r0] str ip, [r0]
.no_outsw_2: tst r2, #1 .Lno_outsw_2: tst r2, #1
ldrne r3, [r1] ldrne r3, [r1]
......
arch/arm/lib/io-writesw-armv4.S
View file @ a9c4814d
...@@ -22,8 +22,8 @@ ...@@ -22,8 +22,8 @@
#endif #endif
.endm .endm
.outsw_align: movs ip, r1, lsl #31 .Loutsw_align: movs ip, r1, lsl #31
bne .outsw_noalign bne .Loutsw_noalign
ldrh r3, [r1], #2 ldrh r3, [r1], #2
sub r2, r2, #1 sub r2, r2, #1
...@@ -33,35 +33,35 @@ ENTRY(__raw_writesw) ...@@ -33,35 +33,35 @@ ENTRY(__raw_writesw)
teq r2, #0 teq r2, #0
moveq pc, lr moveq pc, lr
ands r3, r1, #3 ands r3, r1, #3
bne .outsw_align bne .Loutsw_align
stmfd sp!, {r4, r5, lr} stmfd sp!, {r4, r5, lr}
subs r2, r2, #8 subs r2, r2, #8
bmi .no_outsw_8 bmi .Lno_outsw_8
.outsw_8_lp: ldmia r1!, {r3, r4, r5, ip} .Loutsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
subs r2, r2, #8 subs r2, r2, #8
outword r3 outword r3
outword r4 outword r4
outword r5 outword r5
outword ip outword ip
bpl .outsw_8_lp bpl .Loutsw_8_lp
.no_outsw_8: tst r2, #4 .Lno_outsw_8: tst r2, #4
beq .no_outsw_4 beq .Lno_outsw_4
ldmia r1!, {r3, ip} ldmia r1!, {r3, ip}
outword r3 outword r3
outword ip outword ip
.no_outsw_4: movs r2, r2, lsl #31 .Lno_outsw_4: movs r2, r2, lsl #31
bcc .no_outsw_2 bcc .Lno_outsw_2
ldr r3, [r1], #4 ldr r3, [r1], #4
outword r3 outword r3
.no_outsw_2: ldrneh r3, [r1] .Lno_outsw_2: ldrneh r3, [r1]
strneh r3, [r0] strneh r3, [r0]
ldmfd sp!, {r4, r5, pc} ldmfd sp!, {r4, r5, pc}
...@@ -74,7 +74,8 @@ ENTRY(__raw_writesw) ...@@ -74,7 +74,8 @@ ENTRY(__raw_writesw)
#define push_hbyte1 lsl #8 #define push_hbyte1 lsl #8
#endif #endif
.outsw_noalign: ldr r3, [r1, -r3]! .Loutsw_noalign:
ldr r3, [r1, -r3]!
subcs r2, r2, #1 subcs r2, r2, #1
bcs 2f bcs 2f
subs r2, r2, #2 subs r2, r2, #2
......
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