Commit 83405f05 authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik

[PATCH] skge: fix truncated collision threshold mask

Patch to correct broken collision threshold mask in (same problem
as sky2 driver).  Should be three bits wide, but the mask only allows
for 1 bit to be set.
Signed-off-by: default avatarStephen Hemminger <shemminger@osdl.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent fbb88b3e
...@@ -1734,11 +1734,11 @@ enum { ...@@ -1734,11 +1734,11 @@ enum {
GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
}; };
#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
#define TX_COL_DEF 0x04 #define TX_COL_DEF 0x04 /* late collision after 64 byte */
/* GM_RX_CTRL 16 bit r/w Receive Control Register */ /* GM_RX_CTRL 16 bit r/w Receive Control Register */
enum { enum {
......
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