ARM: DaVinci: gpio support, with irqs

Add basic gpio operations:  get value, set/clear, set direction, and
use gpio as an irq.  Includes irq and clock cleanups, but no muxing
updates (e.g. PINMUX0/PINMUX1 declarations).

Lightly tested; gpio outputs seem to behave, as do IRQs in banks 0 and 2.
The issue with banks 1, 3 and 4 may be just not having found a pin that's
not muxed to some essential purpose, for testing.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@mvista.com>

arch/arm/mach-davinci/Makefile

@@ -5,7 +5,8 @@
 
 
 # Common objects
-obj-y 				:= time.o irq.o dma.o clock.o serial.o io.o devices.o
+obj-y 				:= time.o irq.o dma.o clock.o serial.o io.o \
+					devices.o gpio.o
 
 # Board specific
 obj-$(CONFIG_MACH_DAVINCI_EVM)  	+= board-evm.o i2c-emac.o

arch/arm/mach-davinci/clock.c

@@ -43,7 +43,6 @@
 #include <asm/arch/hardware.h>
 #include "clock.h"
 
-#define DAVINCI_MAX_CLK 9
 
 #define PLL1_PLLM   __REG(0x01c40910)
 #define PLL2_PLLM   __REG(0x01c40D10)
@@ -261,7 +260,7 @@ void clk_unregister(struct clk *clk)
 
 EXPORT_SYMBOL(clk_unregister);
 
-static struct clk davinci_clks[DAVINCI_MAX_CLK] = {
+static struct clk davinci_clks[] = {
 	{
 		.name = "ARMCLK",
 		.rate = &armrate,
@@ -303,6 +302,11 @@ static struct clk davinci_clks[DAVINCI_MAX_CLK] = {
 		.rate = &commonrate,
 		.lpsc = DAVINCI_LPSC_SPI,
 	},
+	{
+		.name = "gpio",
+		.rate = &commonrate,
+		.lpsc = DAVINCI_LPSC_GPIO,
+	},
 	{
 		.name = "AEMIFCLK",
 		.rate = &commonrate,
@@ -319,7 +323,9 @@ int __init davinci_clk_init(void)
 	commonrate = ((PLL1_PLLM + 1) * 27000000) / 6;
 	armrate = ((PLL1_PLLM + 1) * 27000000) / 2;
 
-	for (clkp = davinci_clks; count < DAVINCI_MAX_CLK; count++, clkp++) {
+	for (clkp = davinci_clks;
+			count < ARRAY_SIZE(davinci_clks);
+			count++, clkp++) {
 		clk_register(clkp);
 
 		/* Turn on clocks that have been enabled in the

arch/arm/mach-davinci/gpio.c

+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+
+#include <asm/mach/irq.h>
+
+
+/* create a non-inlined version */
+static struct gpio_controller *__iomem gpio2controller(unsigned gpio)
+{
+	return gpio_to_controller(gpio);
+}
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Assuming the pin is muxed as a gpio output, set its output value.
+ */
+int __gpio_set(unsigned gpio, int value)
+{
+	struct gpio_controller	*__iomem g = gpio2controller(gpio);
+
+	if (!g)
+		return -EINVAL;
+	__raw_writel(gpio_mask(gpio), value ? &g->set_data : &g->clr_data);
+	return 0;
+}
+EXPORT_SYMBOL(__gpio_set);
+
+
+/*
+ * Read the pin's value (works even if it's not set up as output);
+ * returns zero/nonzero.
+ *
+ * Note that changes are synched to the GPIO clock, so reading values back
+ * right after you've set them may give old values.
+ */
+int __gpio_get(unsigned gpio)
+{
+	struct gpio_controller	*__iomem g = gpio2controller(gpio);
+
+	if (!g)
+		return -EINVAL;
+	return !!(gpio_mask(gpio) & __raw_readl(&g->in_data));
+}
+EXPORT_SYMBOL(__gpio_get);
+
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * We expect board setup code to handle all gpio direction setup,
+ * so there's no need to let driver modules do it.
+ *
+ * That same board setup code must also set PINMUX0 and PINMUX1 as
+ * needed, and enable the GPIO clock.
+ */
+int __init gpio_set_direction(unsigned gpio, int is_in)
+{
+	struct gpio_controller	*__iomem g = gpio2controller(gpio);
+	u32			temp;
+	u32			mask;
+
+	if (!g)
+		return -EINVAL;
+
+	g = gpio_to_controller(gpio);
+	mask = gpio_mask(gpio);
+	temp = __raw_readl(&g->dir);
+	if (is_in)
+		temp |= mask;
+	else
+		temp &= ~mask;
+	__raw_writel(temp, &g->dir);
+	return 0;
+}
+EXPORT_SYMBOL(gpio_set_direction);
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * We expect irqs will normally be set up as input pins, but they can also be
+ * used as output pins ... which is convenient for testing.
+ *
+ * NOTE:  GPIO0..GPIO7 also have direct INTC hookups, which work in addition
+ * to their GPIOBNK0 irq (but with a bit less overhead).  But we don't have
+ * a good way to hook those up ...
+ *
+ * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
+ * serve as EDMA event triggers.
+ */
+
+#define	irq2gpio(irq)	((irq) - DAVINCI_N_AINTC_IRQ)
+
+static void gpio_irq_disable(unsigned irq)
+{
+	struct gpio_controller	*__iomem g = get_irq_chipdata(irq);
+	u32			mask = gpio_mask(irq2gpio(irq));
+
+	__raw_writel(mask, &g->clr_falling);
+	__raw_writel(mask, &g->clr_rising);
+}
+
+static void gpio_irq_enable(unsigned irq)
+{
+	struct gpio_controller	*__iomem g = get_irq_chipdata(irq);
+	u32			mask = gpio_mask(irq2gpio(irq));
+
+	if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
+		__raw_writel(mask, &g->set_falling);
+	if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
+		__raw_writel(mask, &g->set_rising);
+}
+
+static int gpio_irq_type(unsigned irq, unsigned trigger)
+{
+	struct gpio_controller	*__iomem g = get_irq_chipdata(irq);
+	unsigned		mask = gpio_mask(irq2gpio(irq));
+
+	if (trigger & ~(IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_EDGE_RISING))
+		return -EINVAL;
+
+	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
+	irq_desc[irq].status |= trigger;
+
+	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
+			? &g->set_falling : &g->clr_falling);
+	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
+			? &g->set_rising : &g->clr_rising);
+	return 0;
+}
+
+static struct irq_chip gpio_irqchip = {
+	.name		= "GPIO",
+	.enable		= gpio_irq_enable,
+	.disable	= gpio_irq_disable,
+	.set_type	= gpio_irq_type,
+	// .set_wake	= ...
+};
+
+static void
+gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+	struct gpio_controller	*__iomem g = get_irq_chipdata(irq);
+	u32			mask = 0xffff;
+
+	/* we only care about one bank */
+	if (irq & 1)
+		mask <<= 16;
+
+	/* temporarily mask (level sensitive) parent IRQ */
+	desc->chip->ack(irq);
+	for (;;) {
+		u32		status;
+		struct irqdesc	*gpio;
+		int		n;
+
+		/* ack any irqs */
+		status = __raw_readl(&g->intstat) & mask;
+		if (!status)
+			break;
+		__raw_writel(status, &g->intstat);
+		if (irq & 1)
+			status >>= 16;
+
+		/* now demux them to the right lowlevel handler */
+		n = (int) get_irq_data(irq);
+		gpio = &irq_desc[n];
+		while (status) {
+			if (status & 1)
+				gpio->handle_irq(n, gpio, regs);
+			n++;
+			gpio++;
+			status >>= 1;
+		}
+	}
+	desc->chip->unmask(irq);
+	/* now it may re-trigger */
+}
+
+/*
+ * NOTE:  for suspend/resume, probably best to make a sysdev (and class)
+ * with its suspend/resume calls hooking into the results of the set_wake()
+ * calls ... so if no gpios are wakeup events the clock can be disabled,
+ * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
+ * can be set appropriately for GPIOV33 pins.
+ */
+
+static int __init davinci_gpio_irq_setup(void)
+{
+	static const char __initdata err1[] =
+			KERN_ERR "Error %ld getting gpio clock?\n";
+	static const char __initdata info1[] =
+			KERN_INFO "DaVinci: %d gpio irqs\n";
+
+	unsigned	gpio, irq, bank;
+	struct clk	*clk;
+
+	clk = clk_get(NULL, "gpio");
+	if (IS_ERR(clk)) {
+		printk(err1, PTR_ERR(clk));
+		return 0;
+	}
+	clk_enable(clk);
+
+	for (gpio = 0, irq = DAVINCI_GPIO_IRQ(0), bank = IRQ_GPIOBNK0;
+			gpio < DAVINCI_N_GPIO;
+			bank++) {
+		struct gpio_controller	*__iomem g = gpio2controller(gpio);
+		unsigned		i;
+
+		__raw_writel(~0, &g->clr_falling);
+		__raw_writel(~0, &g->clr_rising);
+
+		/* set up all irqs in this bank */
+		set_irq_chained_handler(bank, gpio_irq_handler);
+		set_irq_chipdata(bank, g);
+		set_irq_data(bank, (void *) irq);
+
+		for (i = 0;
+				i < 16 && gpio < DAVINCI_N_GPIO;
+				i++, irq++, gpio++) {
+			set_irq_chip(irq, &gpio_irqchip);
+			set_irq_chipdata(irq, g);
+			set_irq_handler(irq, do_simple_IRQ);
+			set_irq_flags(irq, IRQF_VALID);
+		}
+	}
+
+	/* BINTEN -- per-bank interrupt enable. genirq would also let these
+	 * bits be set/cleared dynamically.
+	 */
+	__raw_writel(0x1f, (void *__iomem)
+			IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
+
+	printk(info1, irq - DAVINCI_GPIO_IRQ(0));
+	return 0;
+}
+arch_initcall(davinci_gpio_irq_setup);

arch/arm/mach-davinci/irq.c

@@ -41,10 +41,8 @@
 #include <asm/arch/memory.h>
 #include <asm/arch/hardware.h>
 
-void intcInit(void);
 
-#define INTNUM                      DAVINCI_MAXIRQNUM
-#define EXCNUM                      ( 8 - 1 )
+
 #define INTC_NUM_INTS_ONE_REGISTER  32
 
 #define INTC_CLEAR_INTERRUPTS       0xFFFFFFFF
@@ -54,10 +52,11 @@ void intcInit(void);
 #define INTC_FIQ_ENTRY_RAW				0x1
 #define INTC_VECT_OFFSET				0x100
 
-volatile intc_registers *pintc = (intc_registers *) IO_ADDRESS(DAVINCI_ARM_INTC_BASE);
+static volatile intc_registers *pintc
+		= (intc_registers *) IO_ADDRESS(DAVINCI_ARM_INTC_BASE);
 
 
-void davinci_intcinit(void);
+static void __init davinci_intcinit(void);
 
 /* Disable interrupt */
 static void davinci_xdisable_int(unsigned int intno)
@@ -67,7 +66,7 @@ static void davinci_xdisable_int(unsigned int intno)
 	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
 		mask = 1 << intno;
 		pintc->eint0 &= ~mask;
-	} else if (intno <= INTNUM) {
+	} else if (intno < DAVINCI_N_AINTC_IRQ) {
 		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
 		pintc->eint1 &= ~mask;
 	}
@@ -80,26 +79,27 @@ static void davinci_xenable_int(unsigned int intno)
 	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
 		mask = 1 << intno;
 		pintc->eint0 |= mask;
-	} else if (intno <= INTNUM) {
+	} else if (intno < DAVINCI_N_AINTC_IRQ) {
 		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
 		pintc->eint1 |= mask;
 	}
 }
 
 /* EOI interrupt */
-void davinci_xeoi_pic(unsigned int intno)
+static void davinci_xeoi_pic(unsigned int intno)
 {
 	unsigned int mask;
 	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
 		mask = 1 << intno;
 		pintc->irq0 = mask;
-	} else if (intno < INTNUM) {
+	} else if (intno < DAVINCI_N_AINTC_IRQ) {
 		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
 		pintc->irq1 = mask;
 	}
 }
 
-static struct irqchip irqchip_0 = {
+static struct irq_chip irqchip_0 = {
+	.name = "AINTC",
 	.ack = davinci_xeoi_pic,
 	.mask = davinci_xdisable_int,
 	.unmask = davinci_xenable_int,
@@ -112,9 +112,9 @@ void __init davinci_irq_init(void)
 
 	davinci_intcinit();
 
+	/* set up irq vectors */
 	ptr += INTC_VECT_OFFSET / (sizeof(*ptr));
-
-	for (i = 0; i < INTNUM; i++) {
+	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
 		if (i == 0) {
 			*ptr = 0xFFFFFFFF;
 		} else {
@@ -122,9 +122,9 @@ void __init davinci_irq_init(void)
 		}
 		ptr++;
 	}
-	/* Proggam the irqchip structures for ARM INTC */
 
-	for (i = 0; i < NR_IRQS; i++) {
+	/* Program the irqchip structures for ARM INTC */
+	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
 		set_irq_chip(i, &irqchip_0);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                 if (i != IRQ_TINT1_TINT34)
@@ -134,8 +134,8 @@ void __init davinci_irq_init(void)
 	}
 }
 
-/* Interrupt Controller Initialize */
-void davinci_intcinit(void)
+/* ARM Interrupt Controller Initialize */
+static void __init davinci_intcinit(void)
 {
 	/* Clear all interrupt requests - write 1 to clear the interrupt */
 	pintc->fiq0 = pintc->irq0 = INTC_CLEAR_INTERRUPTS;

include/asm-arm/arch-davinci/gpio.h

+/* include/asm-arm/arch-davinci/gpio.h */
+
+#ifndef	__DAVINCI_GPIO_H
+#define	__DAVINCI_GPIO_H
+
+/*
+ * basic gpio routines
+ *
+ * board-specific init should be done by arch/.../.../board-XXX.c (maybe
+ * initializing banks together) rather than boot loaders; kexec() won't
+ * go through boot loaders.
+ *
+ * the gpio clock will be turned on when gpios are used, and you may also
+ * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
+ * used as gpios, not with other peripherals.
+ *
+ * GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation, and maybe
+ * for later updates, code should write GPIO(N) or:
+ *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
+ *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
+ *
+ * GPIO IRQs all use DAVINCI_GPIO_IRQ(N) or DAVINCI_GPIO_IRQ(GPIOV33(N)) etc
+ * for now, that's != GPIO(N)
+ */
+#define	GPIO(X)		(X)		/* 0 <= X <= 71 */
+#define	GPIOV18(X)	(X)		/* 1.8V i/o; 0 <= X <= 53 */
+#define	GPIOV33(X)	((X)+54)	/* 3.3V i/o; 0 <= X <= 17 */
+
+
+struct gpio_controller {
+	u32	dir;
+	u32	out_data;
+	u32	set_data;
+	u32	clr_data;
+	u32	in_data;
+	u32	set_rising;
+	u32	clr_rising;
+	u32	set_falling;
+	u32	clr_falling;
+	u32	intstat;
+};
+
+
+/* The gpio_to_controller() and gpio_mask() functions inline to constants
+ * with constant parameters; or in outlined code they execute at runtime.
+ *
+ * You'd access the controller directly when reading or writing more than
+ * one gpio value at a time, and to support wired logic where the value
+ * being driven by the cpu need not match the value read back.
+ */
+static inline struct gpio_controller *__iomem
+gpio_to_controller(unsigned gpio)
+{
+	void *__iomem ptr;
+
+	if (gpio < 32)
+		ptr = (void *__iomem) IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
+	else if (gpio < 64)
+		ptr = (void *__iomem) IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
+	else if (gpio < DAVINCI_N_GPIO)
+		ptr = (void *__iomem) IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+	else
+		ptr = NULL;
+	return ptr;
+}
+
+static inline u32 gpio_mask(unsigned gpio)
+{
+	return 1 << (gpio % 32);
+}
+
+
+/* The get/set/clear functions will inline when called with constant
+ * parameters, for low-overhead bitbanging.  Illegal constant parameters
+ * cause link-time errors.
+ *
+ * Otherwise, calls with variable parameters use outlined functions.
+ */
+extern int __error_inval_gpio(void);
+
+extern int __gpio_set(unsigned gpio, int value);
+extern int __gpio_get(unsigned gpio);
+
+static inline int gpio_set(unsigned gpio)
+{
+	struct gpio_controller	*__iomem g;
+
+	if (!__builtin_constant_p(gpio))
+		return __gpio_set(gpio, 1);
+
+	if (gpio >= DAVINCI_N_GPIO)
+		return __error_inval_gpio();
+
+	g = gpio_to_controller(gpio);
+	__raw_writel(gpio_mask(gpio), &g->set_data);
+	return 0;
+}
+
+static inline int gpio_clear(unsigned gpio)
+{
+	struct gpio_controller	*__iomem g;
+
+	if (!__builtin_constant_p(gpio))
+		return __gpio_set(gpio, 1);
+
+	if (gpio >= DAVINCI_N_GPIO)
+		return __error_inval_gpio();
+
+	g = gpio_to_controller(gpio);
+	__raw_writel(gpio_mask(gpio), &g->clr_data);
+	return 0;
+}
+
+static inline int gpio_set_value(unsigned gpio, int value)
+{
+	if (__builtin_constant_p(value)) {
+		if (value)
+			return gpio_set(gpio);
+		else
+			return gpio_clear(gpio);
+	}
+	if (__builtin_constant_p(gpio) && gpio >= DAVINCI_N_GPIO)
+		return __error_inval_gpio();
+
+	return __gpio_set(gpio, value);
+}
+
+/* Returns zero or nonzero, or negative on error; works for gpios
+ * configured as inputs OR as outputs.
+ *
+ * NOTE: changes in reported values are synchronized to the GPIO clock.
+ * This is most easily seen after calls to gpio_set() and gpio_clear(),
+ * where set-then-get might return the old value.
+ */
+static inline int gpio_get_value(unsigned gpio)
+{
+	struct gpio_controller	*__iomem g;
+
+	if (!__builtin_constant_p(gpio))
+		return __gpio_get(gpio);
+
+	if (gpio >= DAVINCI_N_GPIO)
+		return __error_inval_gpio();
+
+	g = gpio_to_controller(gpio);
+	return !!(gpio_mask(gpio) & __raw_readl(&g->in_data));
+}
+
+/* powerup default direction is IN */
+extern int __init gpio_set_direction(unsigned gpio, int is_in);
+
+
+/* NOTE:  currently there's no "claim/release" mechanism for GPIOs,
+ * so drivers arguing over them will get errors much like they will
+ * when the pin isn't muxed properly as gpio ...
+ */
+#endif	/* __DAVINCI_GPIO_H */

include/asm-arm/arch-davinci/irqs.h

@@ -101,11 +101,12 @@
 #define IRQ_COMMRX       62
 #define IRQ_EMUINT       63
 
-#define DAVINCI_MAXIRQNUM  63
-#define NR_IRQS		   (DAVINCI_MAXIRQNUM + 1)
-#define DAVINCI_MAXSWINUM  DAVINCI_MAXIRQNUM
+#define DAVINCI_N_AINTC_IRQ	64
+#define DAVINCI_N_GPIO		71
 
-#define DAVINCI_MAXFIQNUM  0
+#define NR_IRQS			(DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
+
+#define DAVINCI_GPIO_IRQ(n)	(DAVINCI_N_AINTC_IRQ + (n))
 
 #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34