Some minor fixes for audio driver

run a software reset before start to program the registers.
read back the PLL settings to make sure that it took the programming.
Signed-off-by: 薛德章 <frank.xue@neuros.com.cn>
Signed-off-by: Jean-Paul Saman <jpsaman@videolan.org>

drivers/i2c/chips/tlv320aic23.c

@@ -117,6 +117,13 @@ int tlv320aic32_write_value(u8 reg, u16 value)
 
 	return i2c_smbus_write_byte_data(client, reg, val);
 }
+int tlv320aic32_read_value(u8 reg)
+{
+	static struct i2c_client *client;
+	client = new_client;
+
+	return i2c_smbus_read_byte_data(client, reg);
+}
 #endif /* CONFIG_SENSORS_TLV320AIC32 */
 
 static int aic23_detect_client(struct i2c_adapter *adapter, int address,

sound/oss/davinci-audio-aic32.c

@@ -263,6 +263,7 @@ static audio_state_t aic32_state = {
 static struct file_operations *davinci_audio_fops;
 
 int tlv320aic32_write_value(u8 reg, u16 value);
+int tlv320aic32_read_value(u8 reg);
 
 /* TLV320AIC32 write */
 static __inline__ void audio_aic32_write(u8 address, u16 data)
@@ -270,6 +271,53 @@ static __inline__ void audio_aic32_write(u8 address, u16 data)
 	if (tlv320aic32_write_value(address, data) < 0)
 		printk(KERN_INFO "aic32 write failed for reg = %d\n", address);
 }
+static __inline__ int audio_aic32_read(u8 address)
+{
+	int val;
+
+	val = tlv320aic32_read_value(address);
+	if (val < 0)
+		printk(KERN_INFO "aic32 read failed for reg = %d\n", address);
+	return val;
+}
+void aic32_show_registers(void)
+{
+	int pll, p, j, d;
+	int codec_clk_src;
+	int external_clk_src;
+
+	pll = audio_aic32_read(PLL_A_REG) >> 7;
+	p = audio_aic32_read(PLL_A_REG) & 7;
+	j = audio_aic32_read(PLL_B_REG) >> 2;
+	d = (audio_aic32_read(PLL_C_REG) << 6) | (audio_aic32_read(PLL_D_REG) >> 2);
+	codec_clk_src = audio_aic32_read(CODEC_CLKIN_CTRL_REG)&1;
+	
+	printk("debug:\n");
+	if(codec_clk_src == 0)
+	{
+		external_clk_src = (audio_aic32_read(CLOCK_GENERATION_CTRL_REG) << 2) >> 4;
+		if(external_clk_src == 0)
+			printk("aic32 external clock source is MCLK\n");
+		else if(external_clk_src == 2)
+			printk("aic32 external clock source is BCLK\n");
+		printk("Codec Clock source: PLLDIV_OUT\n");
+	}
+	else if(codec_clk_src == 1)
+	{
+		external_clk_src = audio_aic32_read(CLOCK_GENERATION_CTRL_REG) >> 6;
+		if(external_clk_src == 0)
+			printk("aic32 external clock source is MCLK\n");
+		else if(external_clk_src == 2)
+			printk("aic32 external clock source is BCLK\n");
+		printk("Codec Clock source: CLKDIV_OUT\n");
+	}
+
+	printk("PLL enable = %d\n", pll);
+	printk("P-value: %d\n", p);
+	printk("J-value: %d\n", j);
+	printk("D-value: %d\n", d);
+	printk("Fsref = (MCLK * %d.%d * R)/(2048 * %d);\n", j, d, p);
+}
 
 static void enable_adc(void)
 {
@@ -278,6 +326,7 @@ static void enable_adc(void)
 	audio_aic32_write(LINE1R_TO_RIGHT_ADC_CTRL_REG,
 				LINE1R_NOT_CONNECT | RIGHT_ADC_POWER_UP);
 }
+
 /* enable ADC and enable line1 input*/
 static void enable_line1_input(void)
 {
@@ -769,7 +818,6 @@ mixer_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg)
 out:
 	return ret;
 }
-
 int davinci_set_samplerate(long sample_rate)
 {
 	u8 count = 0;
@@ -916,6 +964,8 @@ int davinci_set_samplerate(long sample_rate)
 		audio_aic32_write(PLL_D_REG,
 					LSB6BIT(5635));	/* D-value 6-LSB's */
 
+		udelay(200);
+		aic32_show_registers();
 	}
 
 	else if ((reg_info[count].Fsref == 88200) |
@@ -935,6 +985,9 @@ int davinci_set_samplerate(long sample_rate)
 					MSB8BIT(3802));	/* D-value 8-MSB's */
 		audio_aic32_write(PLL_D_REG,
 					LSB6BIT(3802));	/* D-value 6-LSB's */
+
+		udelay(200);
+		aic32_show_registers();
 	}
 
 #else
@@ -1101,11 +1154,9 @@ static inline void aic32_configure()
 	/* Page select register */
 	audio_aic32_write(PAGE_SELECT_REG, PAGE0);
 
-	/* Self clearing aic32 software reset */
-	audio_aic32_write(SOFT_RESET_REG, SELF_CLEAR_SOFT_RESET);
-
-	/* wait for reset to complete */
-	mdelay(100);
+        /* Self clearing aic32 software reset */
+        audio_aic32_write(SOFT_RESET_REG,
+                          SELF_CLEAR_SOFT_RESET);
 
 	davinci_set_mono_stereo(aic32_local.nochan);