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linux-davinci-2.6.23
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linux
linux-davinci-2.6.23
Commits
7991ec0d
Commit
7991ec0d
authored
Jun 03, 2008
by
吴智聪(John Wu)
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kernel side soft reset bug fix
parent
762a79f1
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1
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-3
arch/arm/mach-davinci/time.c
arch/arm/mach-davinci/time.c
+3
-3
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arch/arm/mach-davinci/time.c
View file @
7991ec0d
...
@@ -336,15 +336,15 @@ void davinci_watchdog_reset(void) {
...
@@ -336,15 +336,15 @@ void davinci_watchdog_reset(void) {
u32
tgcr
,
wdtcr
,
base
=
DAVINCI_WDOG_BASE
;
u32
tgcr
,
wdtcr
,
base
=
DAVINCI_WDOG_BASE
;
/* disable, internal clock source */
/* disable, internal clock source */
davinci_writel
(
0
,
base
+
TCR
);
davinci_writel
(
0
,
base
+
T
G
CR
);
/* reset timer, set mode to 64-bit watchdog, and unreset */
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr
=
0
;
tgcr
=
0
;
davinci_writel
(
tgcr
,
base
+
TCR
);
davinci_writel
(
tgcr
,
base
+
T
G
CR
);
tgcr
=
TGCR_TIMMODE_64BIT_WDOG
<<
TGCR_TIMMODE_SHIFT
;
tgcr
=
TGCR_TIMMODE_64BIT_WDOG
<<
TGCR_TIMMODE_SHIFT
;
tgcr
|=
(
TGCR_UNRESET
<<
TGCR_TIM12RS_SHIFT
)
|
tgcr
|=
(
TGCR_UNRESET
<<
TGCR_TIM12RS_SHIFT
)
|
(
TGCR_UNRESET
<<
TGCR_TIM34RS_SHIFT
);
(
TGCR_UNRESET
<<
TGCR_TIM34RS_SHIFT
);
davinci_writel
(
tgcr
,
base
+
TCR
);
davinci_writel
(
tgcr
,
base
+
T
G
CR
);
/* clear counter and period regs */
/* clear counter and period regs */
davinci_writel
(
0
,
base
+
TIM12
);
davinci_writel
(
0
,
base
+
TIM12
);
...
...
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