ARM: DaVinci: Add read/write[bwl] and _REG* macros.

Signed-off-by: Komal Shah <komal_shah802003@yahoo.com>

include/asm-arm/arch-davinci/io.h

@@ -35,13 +35,12 @@
  * I/O mapping
  * ----------------------------------------------------------------------------
  */
-#define IO_PHYS	     0x01c00000
-#define IO_VIRT	     0xe1000000
-#define IO_SIZE	     0x00400000
-#define io_p2v(pa)   (((pa) & (IO_SIZE-1)) + IO_VIRT)
-#define io_v2p(va)   (((va) & (IO_SIZE-1)) + IO_PHYS)
-#define IO_ADDRESS(x) io_p2v(x)
-#define __REG(x)	(*((volatile unsigned long *)io_p2v(x)))
+#define IO_PHYS	     	0x01c00000
+#define IO_VIRT	     	0xe1000000
+#define IO_SIZE	     	0x00400000
+#define io_p2v(pa)   	(((pa) & (IO_SIZE-1)) + IO_VIRT)
+#define io_v2p(va)   	(((va) & (IO_SIZE-1)) + IO_PHYS)
+#define IO_ADDRESS(x)	io_p2v(x)
 
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
@@ -53,9 +52,47 @@
 #define __mem_isa(a)		(a)
 
 #ifndef __ASSEMBLER__
+
+/*
+ * Functions to access the OMAP IO region
+ *
+ * NOTE: - Use davinci_read/write[bwl] for physical register addresses
+ *	 - Use __raw_read/write[bwl]() for virtual register addresses
+ *	 - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
+ *	 - DO NOT use hardcoded virtual addresses to allow changing the
+ *	   IO address space again if needed
+ */
+#define davinci_readb(a)	(*(volatile unsigned char  *)IO_ADDRESS(a))
+#define davinci_readw(a)	(*(volatile unsigned short *)IO_ADDRESS(a))
+#define davinci_readl(a)	(*(volatile unsigned int   *)IO_ADDRESS(a))
+
+#define davinci_writeb(v,a)	(*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
+#define davinci_writew(v,a)	(*(volatile unsigned short *)IO_ADDRESS(a) = (v))
+#define davinci_writel(v,a)	(*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
+
+/* 16 bit uses LDRH/STRH, base +/- offset_8 */
+typedef struct { volatile u16 offset[256]; } __regbase16;
+#define __REGV16(vaddr)		((__regbase16 *)((vaddr)&~0xff)) \
+					->offset[((vaddr)&0xff)>>1]
+#define __REG16(paddr)          __REGV16(io_p2v(paddr))
+
+/* 8/32 bit uses LDR/STR, base +/- offset_12 */
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+#define __REGV8(vaddr)		((__regbase8  *)((vaddr)&~4095)) \
+					->offset[((vaddr)&4095)>>0]
+#define __REG8(paddr)		__REGV8(io_p2v(paddr))
+
+typedef struct { volatile u32 offset[4096]; } __regbase32;
+#define __REGV32(vaddr)		((__regbase32 *)((vaddr)&~4095)) \
+					->offset[((vaddr)&4095)>>2]
+/* FIXME: Just for compilation sake changed from __REG32 to __REG */
+#define __REG(paddr)		__REGV32(io_p2v(paddr))
+
 extern void davinci_map_common_io(void);
-#endif
+#else
 
-#endif /* __ASM_ARCH_IO_H */
+#define __REG(x)	(*((volatile unsigned long *)io_p2v(x)))
 
+#endif
 
+#endif /* __ASM_ARCH_IO_H */