Skip to content

L
linux-davinci-2.6.23
Commit 68b4855a authored by 张青山(steven.zhang)'s avatar 张青山(steven.zhang)
Browse files
Options

ARM: Davinci: HD FrameBuffer 720p(1280*720) driver support

parent 1d5b8bc6
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 318 additions and 3 deletions
drivers/video/davincifb.c
View file @ 68b4855a
This diff is collapsed.
include/asm-arm/arch-davinci/hardware.h
View file @ 68b4855a
...@@ -49,4 +49,9 @@ ...@@ -49,4 +49,9 @@
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
#define DAVINCI_PHYS_MEM_SIZE 0x10000000
/* 16M reserved for FB driver*/
#define DAVINCI_FB_RESERVE_MEM_SIZE 0x01000000
#define DAVINCI_FB_RESERVE_MEM_BASE (PHYS_OFFSET + \
DAVINCI_PHYS_MEM_SIZE - DAVINCI_FB_RESERVE_MEM_SIZE)
#endif /* __ASM_ARCH_HARDWARE_H */ #endif /* __ASM_ARCH_HARDWARE_H */
include/video/davincifb.h
View file @ 68b4855a
...@@ -15,6 +15,11 @@ ...@@ -15,6 +15,11 @@
#include <linux/fb.h> #include <linux/fb.h>
/* PINMUX0 register */
#define PINMUX0 IO_ADDRESS(0x01c40000)
#define PINMUX0_LOEEN (1 << 24)
#define PINMUX0_LFLDEN (1 << 25)
/* Base registers */ /* Base registers */
#define VPBE_REG_BASE IO_ADDRESS(0x01c72780) #define VPBE_REG_BASE IO_ADDRESS(0x01c72780)
#define VENC_REG_BASE IO_ADDRESS(0x01c72400) #define VENC_REG_BASE IO_ADDRESS(0x01c72400)
...@@ -22,8 +27,8 @@ ...@@ -22,8 +27,8 @@
#define OSD_REG_SIZE 0x00000180 #define OSD_REG_SIZE 0x00000180
/* VPBE Global Registers */ /* VPBE Global Registers */
#define VPBE_PID (VPBE_BASE + 0x0) #define VPBE_PID (VPBE_REG_BASE + 0x0)
#define VPBE_PCR (VPBE_BASE + 0x4) #define VPBE_PCR (VPBE_REG_BASE + 0x4)
/* VPSS Clock Control Register */ /* VPSS Clock Control Register */
#define VPSS_CLKCTL IO_ADDRESS(0x01c40044) #define VPSS_CLKCTL IO_ADDRESS(0x01c40044)
...@@ -202,6 +207,15 @@ ...@@ -202,6 +207,15 @@
#define VENC_VMOD_BLNK (1 << 3) #define VENC_VMOD_BLNK (1 << 3)
#define VENC_VMOD_VIE (1 << 1) #define VENC_VMOD_VIE (1 << 1)
#define VENC_VMOD_VENC (1 << 0) #define VENC_VMOD_VENC (1 << 0)
#define VENC_VIDCTL_VLCKP (1 << 14)
#define VENC_VIDCTL_VLCKE (1 << 13)
#define VENC_VIDCTL_VLCKZ (1 << 12)
#define VENC_VDPRO_CBTYPE (1 << 9)
#define VENC_VDPRO_CBMD (1 << 8)
#define VENC_SYNCCTL_SYSW (1 << 5)
#define VENC_SYNCCTL_SYEV (1 << 1)
#define VENC_SYNCCTL_SYEH (1 << 0)
#define VENC_DCKCTL_DCKEC (1 << 11)
/* other VENC registers' bit positions not defined yet */ /* other VENC registers' bit positions not defined yet */
#define OSD_MODE_CS (1 << 15) #define OSD_MODE_CS (1 << 15)
...@@ -420,6 +434,7 @@ ...@@ -420,6 +434,7 @@
#define LCD 0 #define LCD 0
#define NTSC 1 #define NTSC 1
#define PAL 2 #define PAL 2
#define HD720P 3
#define COMPOSITE 1 #define COMPOSITE 1
#define SVIDEO 2 #define SVIDEO 2
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment