Commit 62922b66 authored by 吴智聪(John Wu)'s avatar 吴智聪(John Wu)

some changes in neuros_ir_blaster driver according to changes in hardware

initialize gpio 47 as output and low,
detect the first wave logic change
parent 765db0a3
...@@ -182,16 +182,14 @@ static void blaster_key(struct blaster_data_pack* blsdat) ...@@ -182,16 +182,14 @@ static void blaster_key(struct blaster_data_pack* blsdat)
} }
return; return;
} }
GPIO23_DIR &= ~GIO_BLS; //gio 47 direction output
GPIO23_CLR_DATA |= GIO_BLS;
/*check if the io port status correct if not correct set it's logic to reverse of start level and hold for a momemt*/ /*check if the io port status correct if not correct set it's logic to reverse of start level and hold for a momemt*/
bitset2 = GPIO23_OUT_DATA; bitset2 = GPIO23_OUT_DATA;
if (((bitset2 & GIO_BLS) != 0) && ((bls_data_pack->bitstimes & BITS_COUNT_MASK) != 0)) if (((bitset2 & GIO_BLS) != 0) && ((bls_data_pack->bitstimes & FIRST_LEVEL_BIT_MASK) != 0))
{ {
GPIO23_CLR_DATA |= GIO_BLS; GPIO23_CLR_DATA |= GIO_BLS;
msleep(WAIT_HARDWARE_RESET); msleep(WAIT_HARDWARE_RESET);
} }
else if (((bitset2 & GIO_BLS) == 0) && ((bls_data_pack->bitstimes & BITS_COUNT_MASK) == 0)) else if (((bitset2 & GIO_BLS) == 0) && ((bls_data_pack->bitstimes & FIRST_LEVEL_BIT_MASK) == 0))
{ {
GPIO23_SET_DATA |= GIO_BLS; GPIO23_SET_DATA |= GIO_BLS;
msleep(WAIT_HARDWARE_RESET); msleep(WAIT_HARDWARE_RESET);
...@@ -276,7 +274,8 @@ static int capture_key(struct blaster_data_type* blsdat) ...@@ -276,7 +274,8 @@ static int capture_key(struct blaster_data_type* blsdat)
if (0 == times++) if (0 == times++)
{ {
blsdat->bitstimes |= ((SET_GPIO01_IN_DATA & GIO_CAP) << 8); if ((GPIO01_IN_DATA & GIO_CAP) == 0)
blsdat->bitstimes |= FIRST_LEVEL_BIT_MASK;
return 0; return 0;
} }
blsdat->bits[times-2] = td; blsdat->bits[times-2] = td;
...@@ -321,7 +320,6 @@ static irqreturn_t handle_bls_timer1_irqs(int irq, void * dev_id) ...@@ -321,7 +320,6 @@ static irqreturn_t handle_bls_timer1_irqs(int irq, void * dev_id)
{ {
disable_irq(IRQ_TINT1_TINT34); disable_irq(IRQ_TINT1_TINT34);
TIMER1_TCR &= ~(3<<22); //disable timer1 34 TIMER1_TCR &= ~(3<<22); //disable timer1 34
GPIO23_DIR |= GIO_BLS; //gio 47 direction input
bls_status = BLS_COMPLETE; bls_status = BLS_COMPLETE;
if (bls_data_pack) if (bls_data_pack)
{ {
...@@ -481,7 +479,8 @@ static int blaster_init( void ) ...@@ -481,7 +479,8 @@ static int blaster_init( void )
PWM0_PER = 709; PWM0_PER = 709;
PWM0_PH1D = 355; PWM0_PH1D = 355;
PWM0_START = 1; PWM0_START = 1;
GPIO23_DIR |= GIO_BLS; //gio 47 direction input GPIO23_DIR &= ~GIO_BLS; //gio 47 direction output
GPIO23_CLR_DATA |= GIO_BLS; //drive the gpio 47 to low
TIMER1_TCR &= ~(3<<22); //disable timer1 34 TIMER1_TCR &= ~(3<<22); //disable timer1 34
ret = request_irq(IRQ_TINT1_TINT34, handle_bls_timer1_irqs,SA_INTERRUPT , "ir_blaster_timer1", &device); //TIMER__INTERRUPT ret = request_irq(IRQ_TINT1_TINT34, handle_bls_timer1_irqs,SA_INTERRUPT , "ir_blaster_timer1", &device); //TIMER__INTERRUPT
disable_irq(IRQ_TINT1_TINT34); disable_irq(IRQ_TINT1_TINT34);
......
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
#define UP_KEY 0x00 #define UP_KEY 0x00
#define GPIO01_DIR __REG(0x01C67010) #define GPIO01_DIR __REG(0x01C67010)
#define SET_GPIO01_IN_DATA __REG(0x01C67020) #define GPIO01_IN_DATA __REG(0x01C67020)
#define SET_GPIO01_RIS_INT __REG(0x01C67024) #define SET_GPIO01_RIS_INT __REG(0x01C67024)
#define CLR_GPIO01_RIS_INT __REG(0x01C67028) #define CLR_GPIO01_RIS_INT __REG(0x01C67028)
#define SET_GPIO01_FAL_INT __REG(0x01C6702C) #define SET_GPIO01_FAL_INT __REG(0x01C6702C)
......
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