Commit 5cedae9c authored by Deepak Saxena's avatar Deepak Saxena Committed by Linus Torvalds

[PATCH] ARM: Fix XScale PMD setting

The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation
defined" and it must be set to zero on Intel XScale CPUs or the cache does
not behave properly. Found by Mike Rapoport while debugging a flash issue
on the PXA255:

	http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 29f767a2
......@@ -376,7 +376,7 @@ void __init build_mem_type_table(void)
ecc_mask = 0;
}
if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) {
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
if (mem_types[i].prot_l1)
mem_types[i].prot_l1 |= PMD_BIT4;
......@@ -631,7 +631,7 @@ void setup_mm_for_reboot(char mode)
pgd = init_mm.pgd;
base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
base_pmdval |= PMD_BIT4;
for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
......
......@@ -127,6 +127,12 @@ static inline int cpu_is_xsc3(void)
}
#endif
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
#define cpu_is_xscale() 0
#else
#define cpu_is_xscale() 1
#endif
#define set_cr(x) \
__asm__ __volatile__( \
"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
......
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