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linux-davinci-2.6.23
Commit 34348012 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 3800/2: S3C2412: DMA channel mappings 

DMA channel mappings for the S3C2312
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 197c9444
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arch/arm/mach-s3c2410/Makefile
View file @ 34348012
......@@ -34,6 +34,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o
obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o
obj-dma-$(CONFIG_CPU_S3C2412) += s3c2412-dma.o
#
# S3C244X support
......
arch/arm/mach-s3c2410/s3c2412-dma.c 0 → 100644
View file @ 34348012
/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c
*
* (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2412 DMA selection
*
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <asm/dma.h>
#include <asm/arch/dma.h>
#include <asm/io.h>
#include "dma.h"
#include "cpu.h"
#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-ac97.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/arch/regs-sdi.h>
#include <asm/arch/regs-iis.h>
#include <asm/arch/regs-spi.h>
#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
[DMACH_XD0] = {
.name = "xdreq0",
.channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
},
[DMACH_XD1] = {
.name = "xdreq1",
.channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
},
[DMACH_SDI] = {
.name = "sdi",
.channels = MAP(S3C2412_DMAREQSEL_SDI),
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_SPI0] = {
.name = "spi0",
.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
},
[DMACH_SPI1] = {
.name = "spi1",
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
},
[DMACH_UART0] = {
.name = "uart0",
.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
},
[DMACH_UART1] = {
.name = "uart1",
.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
},
[DMACH_UART2] = {
.name = "uart2",
.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
},
[DMACH_UART0_SRC2] = {
.name = "uart0",
.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
},
[DMACH_UART1_SRC2] = {
.name = "uart1",
.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
},
[DMACH_UART2_SRC2] = {
.name = "uart2",
.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
},
[DMACH_TIMER] = {
.name = "timer",
.channels = MAP(S3C2412_DMAREQSEL_TIMER),
},
[DMACH_I2S_IN] = {
.name = "i2s-sdi",
.channels = MAP(S3C2412_DMAREQSEL_I2SRX),
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_I2S_OUT] = {
.name = "i2s-sdo",
.channels = MAP(S3C2412_DMAREQSEL_I2STX),
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
},
[DMACH_USB_EP1] = {
.name = "usb-ep1",
.channels = MAP(S3C2412_DMAREQSEL_USBEP1),
},
[DMACH_USB_EP2] = {
.name = "usb-ep2",
.channels = MAP(S3C2412_DMAREQSEL_USBEP2),
},
[DMACH_USB_EP3] = {
.name = "usb-ep3",
.channels = MAP(S3C2412_DMAREQSEL_USBEP3),
},
[DMACH_USB_EP4] = {
.name = "usb-ep4",
.channels = MAP(S3C2412_DMAREQSEL_USBEP4),
},
};
static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
struct s3c24xx_dma_map *map)
{
writel(chan->regs + S3C2412_DMA_DMAREQSEL,
map->channels[0] | S3C2412_DMAREQSEL_HW);
}
static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
.select = s3c2412_dma_select,
.dcon_mask = 0,
.map = s3c2412_dma_mappings,
.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
};
static int s3c2412_dma_add(struct sys_device *sysdev)
{
return s3c24xx_dma_init_map(&s3c2412_dma_sel);
}
static struct sysdev_driver s3c2412_dma_driver = {
.add = s3c2412_dma_add,
};
static int __init s3c2412_dma_init(void)
{
return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
}
arch_initcall(s3c2412_dma_init);
include/asm-arm/arch-s3c2410/dma.h
View file @ 34348012
......@@ -48,6 +48,9 @@ enum dma_ch {
DMACH_USB_EP2,
DMACH_USB_EP3,
DMACH_USB_EP4,
DMACH_UART0_SRC2, /* s3c2412 second uart sources */
DMACH_UART1_SRC2,
DMACH_UART2_SRC2,
DMACH_MAX, /* the end entry */
};
......@@ -317,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
#define S3C2410_DMA_DCSRC (0x18)
#define S3C2410_DMA_DCDST (0x1C)
#define S3C2410_DMA_DMASKTRIG (0x20)
#define S3C2412_DMA_DMAREQSEL (0x24)
#define S3C2410_DISRCC_INC (1<<0)
#define S3C2410_DISRCC_APB (1<<1)
......@@ -383,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
#endif
#ifdef CONFIG_CPU_S3C2412
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
#define S3C2412_DMAREQSEL_HW (1)
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
#endif
#endif /* __ASM_ARCH_DMA_H */
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