Initial audio clock generation register.

CODEC_CLKIN and PLLCLK_IN register are not initialized and
PLL Q,P,J,D value are wrong, cause audio clock is wrong.
This patch initialize PLLCLK_IN uses MCLK, Codec uses PLLDIV_OUT.

sound/oss/davinci-aic32.h

@@ -67,6 +67,9 @@
 #define LEFTLOP_LEVEL_CTRL_REG 86
 #define RIGHTLOP_LEVEL_CTRL_REG 93
 
+#define CODEC_CLKIN_CTRL_REG 101
+#define CLOCK_GENERATION_CTRL_REG 102
+
 /* aic32 control registers value */
 #define PAGE0   0x0