Commit 30729968 authored by 薛德章's avatar 薛德章

Initial audio clock generation register.

CODEC_CLKIN and PLLCLK_IN register are not initialized and
PLL Q,P,J,D value are wrong, cause audio clock is wrong.
This patch initialize PLLCLK_IN uses MCLK, Codec uses PLLDIV_OUT.
parent c254a3d6
...@@ -67,6 +67,9 @@ ...@@ -67,6 +67,9 @@
#define LEFTLOP_LEVEL_CTRL_REG 86 #define LEFTLOP_LEVEL_CTRL_REG 86
#define RIGHTLOP_LEVEL_CTRL_REG 93 #define RIGHTLOP_LEVEL_CTRL_REG 93
#define CODEC_CLKIN_CTRL_REG 101
#define CLOCK_GENERATION_CTRL_REG 102
/* aic32 control registers value */ /* aic32 control registers value */
#define PAGE0 0x0 #define PAGE0 0x0
......
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