Commit 2925aba4 authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] Cleanup memory managment initialization.

Historically plat_mem_setup did the entire platform initialization.  This
was rather impractical because it meant plat_mem_setup had to get away
without any kind of memory allocator.  To keep old code from breaking
plat_setup was just renamed to plat_setup and a second platform
initialization hook for anything else was introduced.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 7ab2dc41
......@@ -55,7 +55,7 @@ extern void au1xxx_time_init(void);
extern void au1xxx_timer_setup(struct irqaction *irq);
extern void set_cpuspec(void);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
struct cpu_spec *sp;
char *argptr;
......
......@@ -120,7 +120,7 @@ static struct pci_controller cobalt_pci_controller = {
.io_offset = 0 - GT64111_IO_BASE
};
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
......
......@@ -86,7 +86,7 @@ static void __init ddb_time_init(void)
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
set_io_port_base(NILE4_PCI_IO_BASE);
isa_slot_offset = NILE4_PCI_MEM_BASE;
......
......@@ -150,7 +150,7 @@ static struct {
static void ddb5476_board_init(void);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
......
......@@ -171,7 +171,7 @@ static void ddb5477_board_init(void);
extern struct pci_controller ddb5477_ext_controller;
extern struct pci_controller ddb5477_io_controller;
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
/* initialize board - we don't trust the loader */
ddb5477_board_init();
......
......@@ -147,7 +147,7 @@ static void __init dec_be_init(void)
extern void dec_time_init(void);
extern void dec_timer_setup(struct irqaction *);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
board_be_init = dec_be_init;
board_time_init = dec_time_init;
......
......@@ -55,7 +55,7 @@ extern void mips_reboot_setup(void);
unsigned char mac_0_1[12];
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned int config = read_c0_config();
unsigned int status = read_c0_status();
......
......@@ -71,7 +71,7 @@ unsigned long __init prom_free_prom_memory(void)
*/
extern void gt64120_time_init(void);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
_machine_restart = galileo_machine_restart;
_machine_halt = galileo_machine_halt;
......
......@@ -152,7 +152,7 @@ void PMON_v2_setup()
gt64120_base = 0xe0000000;
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
unsigned int tmpword;
......
......@@ -154,7 +154,7 @@ void __init it8172_init_ram_resource(unsigned long memsize)
it8172_resources.ram.end = memsize;
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned short dsr;
char *argptr;
......
......@@ -52,7 +52,7 @@ static struct resource jazz_io_resources[] = {
{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
};
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
int i;
......
......@@ -238,7 +238,7 @@ static void jmr3927_board_init(void);
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
char *argptr;
......
......@@ -442,6 +442,48 @@ static inline void bootmem_init(void)
#endif /* CONFIG_BLK_DEV_INITRD */
}
/*
* arch_mem_init - initialize memory managment subsystem
*
* o plat_mem_setup() detects the memory configuration and will record detected
* memory areas using add_memory_region.
* o parse_cmdline_early() parses the command line for mem= options which,
* iff detected, will override the results of the automatic detection.
*
* At this stage the memory configuration of the system is known to the
* kernel but generic memory managment system is still entirely uninitialized.
*
* o bootmem_init()
* o sparse_init()
* o paging_init()
*
* At this stage the bootmem allocator is ready to use.
*
* NOTE: historically plat_mem_setup did the entire platform initialization.
* This was rather impractical because it meant plat_mem_setup had to
* get away without any kind of memory allocator. To keep old code from
* breaking plat_setup was just renamed to plat_setup and a second platform
* initialization hook for anything else was introduced.
*/
extern void plat_mem_setup(void);
static void __init arch_mem_init(char **cmdline_p)
{
/* call board setup routine */
plat_mem_setup();
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_cmdline_early();
bootmem_init();
sparse_init();
paging_init();
}
static inline void resource_init(void)
{
int i;
......@@ -495,8 +537,6 @@ static inline void resource_init(void)
#undef MAXMEM
#undef MAXMEM_PFN
extern void plat_setup(void);
void __init setup_arch(char **cmdline_p)
{
cpu_probe();
......@@ -511,18 +551,8 @@ void __init setup_arch(char **cmdline_p)
#endif
#endif
/* call board setup routine */
plat_setup();
arch_mem_init(cmdline_p);
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_cmdline_early();
bootmem_init();
sparse_init();
paging_init();
resource_init();
#ifdef CONFIG_SMP
plat_smp_setup();
......
......@@ -155,7 +155,7 @@ void __init serial_init(void)
}
#endif
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
int i;
lasat_misc = &lasat_misc_info[mips_machtype];
......
......@@ -50,7 +50,7 @@ const char *get_system_type(void)
return "MIPS Atlas";
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
mips_pcibios_init();
......
......@@ -111,7 +111,7 @@ void __init fd_activate(void)
}
#endif
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned int i;
......
......@@ -45,7 +45,7 @@ const char *get_system_type(void)
return "MIPS SEAD";
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
ioport_resource.end = 0x7fffffff;
......
......@@ -50,7 +50,7 @@ const char *get_system_type(void)
return "MIPSsim";
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
set_io_port_base(0xbfd00000);
......
......@@ -359,7 +359,7 @@ static __init int __init ja_pci_init(void)
arch_initcall(ja_pci_init);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned int tmpword;
......
......@@ -313,7 +313,7 @@ static __init int __init ja_pci_init(void)
arch_initcall(ja_pci_init);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned int tmpword;
......
......@@ -231,7 +231,7 @@ void momenco_time_init(void)
rtc_mips_set_time = m48t37y_set_time;
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
unsigned int tmpword;
......
......@@ -162,7 +162,7 @@ static void __init setup_l3cache(unsigned long size)
printk("Done\n");
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
unsigned int tmpword;
......
......@@ -99,7 +99,7 @@ unsigned long get_system_mem_size(void)
int pnx8550_console_port = -1;
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
int i;
char* argptr;
......
......@@ -218,7 +218,7 @@ static void __init py_late_time_init(void)
py_rtc_setup();
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
board_time_init = yosemite_time_init;
late_time_init = py_late_time_init;
......
......@@ -20,7 +20,7 @@ static void __init qemu_timer_setup(struct irqaction *irq)
setup_irq(0, irq);
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
set_io_port_base(QEMU_PORT_BASE);
board_timer_setup = qemu_timer_setup;
......
......@@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break);
extern void ip22_be_init(void) __init;
extern void ip22_time_init(void) __init;
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
char *ctype;
char *cserial;
......
......@@ -196,7 +196,7 @@ extern void ip27_setup_console(void);
extern void ip27_time_init(void);
extern void ip27_reboot_setup(void);
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
hubreg_t p, e, n_mode;
nasid_t nid;
......
......@@ -87,7 +87,7 @@ void __init ip32_timer_setup(struct irqaction *irq)
setup_irq(IP32_R4K_TIMER_IRQ, irq);
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
board_be_init = ip32_be_init;
......
......@@ -103,7 +103,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
bcm1480_setup();
......
......@@ -252,7 +252,7 @@ static inline void sni_pcimt_time_init(void)
rtc_mips_set_time = mc146818_set_rtc_mmss;
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
sni_pcimt_detect();
sni_pcimt_sc_init();
......
......@@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(void)
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
board_time_init = tx4927_time_init;
board_timer_setup = tx4927_timer_setup;
......
......@@ -61,7 +61,7 @@ tx4938_write_buffer_flush(void)
}
void __init
plat_setup(void)
plat_mem_setup(void)
{
board_time_init = tx4938_time_init;
board_timer_setup = tx4938_timer_setup;
......
......@@ -58,7 +58,7 @@ static void __init timer_init(void)
board_timer_setup = setup_timer_irq;
}
void __init plat_setup(void)
void __init plat_mem_setup(void)
{
vr41xx_calculate_clock_frequency();
......
......@@ -258,4 +258,10 @@ extern char arcs_cmdline[CL_SIZE];
* Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
/*
* Platform memory detection hook called by setup_arch
*/
extern void plat_mem_setup(void);
#endif /* _ASM_BOOTINFO_H */
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