Commit 1ec42c0c authored by Russell King's avatar Russell King

[PATCH] ARM: Remove argument for disable_irq/enable_irq

Since we do not require a register for these operations, we can
remove this unnecessary argument.
Signed-off-by: default avatarRussell King <rmk@arm.linux.org.uk>
parent 7933523d
...@@ -118,7 +118,7 @@ __dabt_svc: ...@@ -118,7 +118,7 @@ __dabt_svc:
@ @
@ IRQs off again before pulling preserved data off the stack @ IRQs off again before pulling preserved data off the stack
@ @
disable_irq r0 disable_irq
@ @
@ restore SPSR and restart the instruction @ restore SPSR and restart the instruction
...@@ -198,7 +198,7 @@ __und_svc: ...@@ -198,7 +198,7 @@ __und_svc:
@ @
@ IRQs off again before pulling preserved data off the stack @ IRQs off again before pulling preserved data off the stack
@ @
1: disable_irq r0 1: disable_irq
@ @
@ restore SPSR and restart the instruction @ restore SPSR and restart the instruction
...@@ -232,7 +232,7 @@ __pabt_svc: ...@@ -232,7 +232,7 @@ __pabt_svc:
@ @
@ IRQs off again before pulling preserved data off the stack @ IRQs off again before pulling preserved data off the stack
@ @
disable_irq r0 disable_irq
@ @
@ restore SPSR and restart the instruction @ restore SPSR and restart the instruction
...@@ -316,7 +316,7 @@ __dabt_usr: ...@@ -316,7 +316,7 @@ __dabt_usr:
@ @
@ IRQs on, then call the main handler @ IRQs on, then call the main handler
@ @
enable_irq r2 enable_irq
mov r2, sp mov r2, sp
adr lr, ret_from_exception adr lr, ret_from_exception
b do_DataAbort b do_DataAbort
...@@ -418,7 +418,7 @@ call_fpe: ...@@ -418,7 +418,7 @@ call_fpe:
movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
bcs iwmmxt_task_enable bcs iwmmxt_task_enable
#endif #endif
enable_irq r7 enable_irq
add pc, pc, r8, lsr #6 add pc, pc, r8, lsr #6
mov r0, r0 mov r0, r0
...@@ -472,7 +472,7 @@ fpundefinstr: ...@@ -472,7 +472,7 @@ fpundefinstr:
__pabt_usr: __pabt_usr:
usr_entry abt usr_entry abt
enable_irq r0 @ Enable interrupts enable_irq @ Enable interrupts
mov r0, r2 @ address (pc) mov r0, r2 @ address (pc)
mov r1, sp @ regs mov r1, sp @ regs
bl do_PrefetchAbort @ call abort handler bl do_PrefetchAbort @ call abort handler
......
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
* stack. * stack.
*/ */
ret_fast_syscall: ret_fast_syscall:
disable_irq r1 @ disable interrupts disable_irq @ disable interrupts
ldr r1, [tsk, #TI_FLAGS] ldr r1, [tsk, #TI_FLAGS]
tst r1, #_TIF_WORK_MASK tst r1, #_TIF_WORK_MASK
bne fast_work_pending bne fast_work_pending
...@@ -49,7 +49,7 @@ work_pending: ...@@ -49,7 +49,7 @@ work_pending:
mov r0, sp @ 'regs' mov r0, sp @ 'regs'
mov r2, why @ 'syscall' mov r2, why @ 'syscall'
bl do_notify_resume bl do_notify_resume
disable_irq r1 @ disable interrupts disable_irq @ disable interrupts
b no_work_pending b no_work_pending
work_resched: work_resched:
...@@ -59,7 +59,7 @@ work_resched: ...@@ -59,7 +59,7 @@ work_resched:
*/ */
ENTRY(ret_to_user) ENTRY(ret_to_user)
ret_slow_syscall: ret_slow_syscall:
disable_irq r1 @ disable interrupts disable_irq @ disable interrupts
ldr r1, [tsk, #TI_FLAGS] ldr r1, [tsk, #TI_FLAGS]
tst r1, #_TIF_WORK_MASK tst r1, #_TIF_WORK_MASK
bne work_pending bne work_pending
...@@ -126,7 +126,7 @@ ENTRY(vector_swi) ...@@ -126,7 +126,7 @@ ENTRY(vector_swi)
ldr ip, [ip] ldr ip, [ip]
mcr p15, 0, ip, c1, c0 @ update control register mcr p15, 0, ip, c1, c0 @ update control register
#endif #endif
enable_irq ip enable_irq
str r4, [sp, #-S_OFF]! @ push fifth arg str r4, [sp, #-S_OFF]! @ push fifth arg
......
...@@ -63,25 +63,21 @@ ...@@ -63,25 +63,21 @@
#define S_R0 0 #define S_R0 0
#define S_OFF 8 #define S_OFF 8
.macro set_cpsr_c, reg, mode
msr cpsr_c, \mode
.endm
#if __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 6
.macro disable_irq, temp .macro disable_irq
cpsid i cpsid i
.endm .endm
.macro enable_irq, temp .macro enable_irq
cpsie i cpsie i
.endm .endm
#else #else
.macro disable_irq, temp .macro disable_irq
set_cpsr_c \temp, #PSR_I_BIT | MODE_SVC msr cpsr_c, #PSR_I_BIT | SVC_MODE
.endm .endm
.macro enable_irq, temp .macro enable_irq
set_cpsr_c \temp, #MODE_SVC msr cpsr_c, #SVC_MODE
.endm .endm
#endif #endif
......
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