[PATCH] mips: add support for Qemu system architecture

Add support for the virtual MIPS system that is emulated by Qemu.  See
http://www.linux-mips.org/wiki/Qemu for a detailed current status.
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/mips/Kconfig

@@ -445,6 +445,24 @@ config DDB5477_BUS_FREQUENCY
 	depends on DDB5477
 	default 0
 
+config QEMU
+	bool "Support for Qemu"
+	select DMA_COHERENT
+	select GENERIC_ISA_DMA
+	select HAVE_STD_PC_SERIAL_PORT
+	select I8259
+	select ISA
+	select SWAP_IO_SPACE
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	help
+	 Qemu is a software emulator which among other architectures also
+	 can simulate a MIPS32 4Kc system.  This patch adds support for the
+	 system architecture that currently is being simulated by Qemu.  It
+	 will eventually be removed again when Qemu has the capability to
+	 simulate actual MIPS hardware platforms.  More information on Qemu
+	 can be found at http://www.linux-mips.org/wiki/Qemu.
+
 config SGI_IP22
 	bool "Support for SGI IP22 (Indy/Indigo2)"
 	select ARC

arch/mips/Makefile

@@ -423,6 +423,12 @@ core-$(CONFIG_PMC_YOSEMITE)	+= arch/mips/pmc-sierra/yosemite/
 cflags-$(CONFIG_PMC_YOSEMITE)	+= -Iinclude/asm-mips/mach-yosemite
 load-$(CONFIG_PMC_YOSEMITE)	+= 0xffffffff80100000
 
+# Qemu simulating MIPS32 4Kc
+#
+core-$(CONFIG_QEMU)		+= arch/mips/qemu/
+cflags-$(CONFIG_QEMU)		+= -Iinclude/asm-mips/mach-qemu
+load-$(CONFIG_QEMU)		+= 0xffffffff80010000
+
 #
 # Momentum Ocelot-3
 #

arch/mips/qemu/Makefile

+#
+# Makefile for Qemu specific kernel interface routines under Linux.
+#
+
+obj-y		= q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o

arch/mips/qemu/q-firmware.c

+#include <linux/init.h>
+#include <asm/bootinfo.h>
+
+void __init prom_init(void)
+{
+	add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
+}

arch/mips/qemu/q-int.S

+/*
+ * Qemu interrupt handler code.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.align	5
+	NESTED(qemu_handle_int, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+	move	a0, sp
+	PTR_LA	ra, ret_from_irq
+	j	do_qemu_int
+	END(qemu_handle_int)

arch/mips/qemu/q-irq.c

+#include <linux/init.h>
+#include <linux/linkage.h>
+
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+#include <asm/qemu.h>
+#include <asm/system.h>
+#include <asm/time.h>
+
+extern asmlinkage void qemu_handle_int(void);
+
+asmlinkage void do_qemu_int(struct pt_regs *regs)
+{
+	unsigned int pending = read_c0_status() & read_c0_cause();
+
+	if (pending & 0x8000) {
+		ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs);
+		return;
+	}
+	if (pending & 0x0400) {
+		int irq = i8259_irq();
+
+		if (likely(irq >= 0))
+			do_IRQ(irq, regs);
+
+		return;
+	}
+}
+
+void __init arch_init_irq(void)
+{
+	set_except_vector(0, qemu_handle_int);
+	mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK;		/* 100MHz */
+
+	init_i8259_irqs();
+	set_c0_status(0x8400);
+}

arch/mips/qemu/q-mem.c

+#include <linux/init.h>
+
+unsigned long __init prom_free_prom_memory(void)
+{
+	return 0UL;
+}

arch/mips/qemu/q-setup.c

+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/time.h>
+
+#define QEMU_PORT_BASE 0xb4000000
+
+static void __init qemu_timer_setup(struct irqaction *irq)
+{
+	/* set the clock to 100 Hz */
+	outb_p(0x34,0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
+	outb_p(LATCH & 0xff , 0x40);	/* LSB */
+	outb(LATCH >> 8 , 0x40);	/* MSB */
+	setup_irq(0, irq);
+}
+
+void __init plat_setup(void)
+{
+	set_io_port_base(QEMU_PORT_BASE);
+	board_timer_setup = qemu_timer_setup;
+}

include/asm-mips/mach-qemu/cpu-feature-overrides.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
+ */
+#define cpu_has_mips16		0
+#define cpu_has_divec		0
+#define cpu_has_cache_cdex_p	0
+#define cpu_has_prefetch	0
+#define cpu_has_mcheck		0
+#define cpu_has_ejtag		0
+
+#define cpu_has_llsc		1
+#define cpu_has_vtag_icache	0
+#define cpu_has_dc_aliases	(PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc	0
+
+#define cpu_has_dsp		0
+
+#define cpu_has_nofpuex		0
+#define cpu_has_64bits		0
+
+#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */

include/asm-mips/mach-qemu/param.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_PARAM_H
+#define __ASM_MACH_QEMU_PARAM_H
+
+#define HZ		100		/* Internal kernel timer frequency */
+
+#endif /* __ASM_MACH_QEMU_PARAM_H */

include/asm-mips/qemu.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_QEMU_H
+#define __ASM_QEMU_H
+
+/*
+ * Interrupt numbers
+ */
+#define Q_PIC_IRQ_BASE		0
+#define Q_COUNT_COMPARE_IRQ	16
+
+/*
+ * Qemu clock rate.  Unlike on real MIPS this has no relation to the
+ * instruction issue rate, so the choosen value is pure fiction, just needs
+ * to match the value in Qemu itself.
+ */
+#define QEMU_C0_COUNTER_CLOCK	100000000
+
+#endif /* __ASM_QEMU_H */