Commit 01b9c414 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King

[ARM] 2856/1: S3C2440 - show DVS status at startup

Patch from Ben Dooks

Show the state of DVS (Dynamic Voltage Scaling) when
starting up on the S3C2440
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d6b0bf21
...@@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = { ...@@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = {
static int s3c2440_clk_add(struct sys_device *sysdev) static int s3c2440_clk_add(struct sys_device *sysdev)
{ {
unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
struct clk *clk_h; struct clk *clk_h;
struct clk *clk_p; struct clk *clk_p;
struct clk *clk_xtal; struct clk *clk_xtal;
...@@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_device *sysdev) ...@@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
print_mhz(s3c2440_clk_upll.rate)); print_mhz(s3c2440_clk_upll.rate),
(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
clk_p = clk_get(NULL, "pclk"); clk_p = clk_get(NULL, "pclk");
clk_h = clk_get(NULL, "hclk"); clk_h = clk_get(NULL, "hclk");
......
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