vlynq_fck is a clksel clock.  But omap2_clk_set_parent() is missing
the code to divide its parent's rate down appropriately when vlynq_fck
is set to use a core_ck parent.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>