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videolan
libva
Commits
d934d2bd
Commit
d934d2bd
authored
May 17, 2011
by
Xiang, Haihao
Browse files
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Plain Diff
i965_drv_video: Ivybridge PCI IDs
Signed-off-by:
Xiang, Haihao
<
haihao.xiang@intel.com
>
parent
88931373
Changes
6
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Showing
6 changed files
with
49 additions
and
19 deletions
+49
-19
i965_drv_video/i965_defines.h
i965_drv_video/i965_defines.h
+2
-1
i965_drv_video/i965_drv_video.c
i965_drv_video/i965_drv_video.c
+20
-10
i965_drv_video/i965_post_processing.c
i965_drv_video/i965_post_processing.c
+6
-3
i965_drv_video/i965_render.c
i965_drv_video/i965_render.c
+8
-4
i965_drv_video/intel_batchbuffer.c
i965_drv_video/intel_batchbuffer.c
+2
-1
i965_drv_video/intel_driver.h
i965_drv_video/intel_driver.h
+11
-0
No files found.
i965_drv_video/i965_defines.h
View file @
d934d2bd
...
@@ -546,7 +546,8 @@
...
@@ -546,7 +546,8 @@
#define MFX_SURFACE_PLANAR_420_8 4
#define MFX_SURFACE_PLANAR_420_8 4
#define MFX_SURFACE_MONOCHROME 12
#define MFX_SURFACE_MONOCHROME 12
#define URB_SIZE(intel) (IS_GEN6(intel->device_id) ? 1024 : \
#define URB_SIZE(intel) (IS_GEN7(intel->device_id) ? 4096 : \
IS_GEN6(intel->device_id) ? 1024 : \
IS_IRONLAKE(intel->device_id) ? 1024 : \
IS_IRONLAKE(intel->device_id) ? 1024 : \
IS_G4X(intel->device_id) ? 384 : 256)
IS_G4X(intel->device_id) ? 384 : 256)
...
...
i965_drv_video/i965_drv_video.c
View file @
d934d2bd
...
@@ -49,18 +49,25 @@
...
@@ -49,18 +49,25 @@
#define HAS_MPEG2(ctx) (IS_G4X((ctx)->intel.device_id) || \
#define HAS_MPEG2(ctx) (IS_G4X((ctx)->intel.device_id) || \
IS_IRONLAKE((ctx)->intel.device_id) || \
IS_IRONLAKE((ctx)->intel.device_id) || \
(IS_GEN6((ctx)->intel.device_id) && (ctx)->intel.has_bsd))
((IS_GEN6((ctx)->intel.device_id) || \
IS_GEN7((ctx)->intel.device_id)) && \
(ctx)->intel.has_bsd))
#define HAS_H264(ctx) ((IS_GEN6((ctx)->intel.device_id) || \
#define HAS_H264(ctx) ((IS_GEN7((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id) || \
IS_IRONLAKE((ctx)->intel.device_id)) && \
IS_IRONLAKE((ctx)->intel.device_id)) && \
(ctx)->intel.has_bsd)
(ctx)->intel.has_bsd)
#define HAS_VC1(ctx) (IS_GEN6((ctx)->intel.device_id) && (ctx)->intel.has_bsd)
#define HAS_VC1(ctx) ((IS_GEN7((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id)) && \
(ctx)->intel.has_bsd)
#define HAS_TILED_SURFACE(ctx) (IS_GEN6((ctx)->intel.device_id) && \
#define HAS_TILED_SURFACE(ctx) ((IS_GEN7((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id)) && \
(ctx)->render_state.interleaved_uv)
(ctx)->render_state.interleaved_uv)
#define HAS_ENCODER(ctx) (IS_GEN6((ctx)->intel.device_id) && \
#define HAS_ENCODER(ctx) ((IS_GEN7((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id)) && \
(ctx)->intel.has_bsd)
(ctx)->intel.has_bsd)
enum
{
enum
{
...
@@ -465,7 +472,8 @@ i965_CreateSurfaces(VADriverContextP ctx,
...
@@ -465,7 +472,8 @@ i965_CreateSurfaces(VADriverContextP ctx,
obj_surface
->
orig_width
=
width
;
obj_surface
->
orig_width
=
width
;
obj_surface
->
orig_height
=
height
;
obj_surface
->
orig_height
=
height
;
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
{
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
{
obj_surface
->
width
=
ALIGN
(
obj_surface
->
orig_width
,
128
);
obj_surface
->
width
=
ALIGN
(
obj_surface
->
orig_width
,
128
);
obj_surface
->
height
=
ALIGN
(
obj_surface
->
orig_height
,
32
);
obj_surface
->
height
=
ALIGN
(
obj_surface
->
orig_height
,
32
);
}
else
{
}
else
{
...
@@ -826,7 +834,7 @@ i965_CreateContext(VADriverContextP ctx,
...
@@ -826,7 +834,7 @@ i965_CreateContext(VADriverContextP ctx,
render_state
->
interleaved_uv
=
1
;
render_state
->
interleaved_uv
=
1
;
break
;
break
;
default:
default:
render_state
->
interleaved_uv
=
!!
IS_GEN6
(
i965
->
intel
.
device_id
);
render_state
->
interleaved_uv
=
!!
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
)
);
break
;
break
;
}
}
...
@@ -1640,6 +1648,8 @@ i965_Init(VADriverContextP ctx)
...
@@ -1640,6 +1648,8 @@ i965_Init(VADriverContextP ctx)
i965
->
codec_info
=
&
ironlake_hw_codec_info
;
i965
->
codec_info
=
&
ironlake_hw_codec_info
;
else
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
else
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
i965
->
codec_info
=
&
gen6_hw_codec_info
;
i965
->
codec_info
=
&
gen6_hw_codec_info
;
else
if
(
IS_GEN7
(
i965
->
intel
.
device_id
))
i965
->
codec_info
=
&
gen6_hw_codec_info
;
else
else
return
VA_STATUS_ERROR_UNKNOWN
;
return
VA_STATUS_ERROR_UNKNOWN
;
...
...
i965_drv_video/i965_post_processing.c
View file @
d934d2bd
...
@@ -42,7 +42,8 @@
...
@@ -42,7 +42,8 @@
#include "i965_render.h"
#include "i965_render.h"
#define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
#define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id))
IS_GEN6((ctx)->intel.device_id) || \
IS_GEN7((ctx)->intel.device_id))
static
const
uint32_t
pp_null_gen5
[][
4
]
=
{
static
const
uint32_t
pp_null_gen5
[][
4
]
=
{
#include "shaders/post_processing/null.g4b.gen5"
#include "shaders/post_processing/null.g4b.gen5"
...
@@ -2242,7 +2243,8 @@ i965_post_processing_internal(VADriverContextP ctx,
...
@@ -2242,7 +2243,8 @@ i965_post_processing_internal(VADriverContextP ctx,
{
{
struct
i965_driver_data
*
i965
=
i965_driver_data
(
ctx
);
struct
i965_driver_data
*
i965
=
i965_driver_data
(
ctx
);
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
gen6_post_processing
(
ctx
,
surface
,
input
,
gen6_post_processing
(
ctx
,
surface
,
input
,
srcx
,
srcy
,
srcw
,
srch
,
srcx
,
srcy
,
srcw
,
srch
,
destx
,
desty
,
destw
,
desth
,
destx
,
desty
,
destw
,
desth
,
...
@@ -2376,7 +2378,8 @@ i965_post_processing_init(VADriverContextP ctx)
...
@@ -2376,7 +2378,8 @@ i965_post_processing_init(VADriverContextP ctx)
assert
(
NUM_PP_MODULES
==
ARRAY_ELEMS
(
pp_modules_gen5
));
assert
(
NUM_PP_MODULES
==
ARRAY_ELEMS
(
pp_modules_gen5
));
assert
(
NUM_PP_MODULES
==
ARRAY_ELEMS
(
pp_modules_gen6
));
assert
(
NUM_PP_MODULES
==
ARRAY_ELEMS
(
pp_modules_gen6
));
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
memcpy
(
pp_context
->
pp_modules
,
pp_modules_gen6
,
sizeof
(
pp_context
->
pp_modules
));
memcpy
(
pp_context
->
pp_modules
,
pp_modules_gen6
,
sizeof
(
pp_context
->
pp_modules
));
else
if
(
IS_IRONLAKE
(
i965
->
intel
.
device_id
))
else
if
(
IS_IRONLAKE
(
i965
->
intel
.
device_id
))
memcpy
(
pp_context
->
pp_modules
,
pp_modules_gen5
,
sizeof
(
pp_context
->
pp_modules
));
memcpy
(
pp_context
->
pp_modules
,
pp_modules_gen5
,
sizeof
(
pp_context
->
pp_modules
));
...
...
i965_drv_video/i965_render.c
View file @
d934d2bd
...
@@ -1299,7 +1299,8 @@ i965_clear_dest_region(VADriverContextP ctx)
...
@@ -1299,7 +1299,8 @@ i965_clear_dest_region(VADriverContextP ctx)
br13
|=
pitch
;
br13
|=
pitch
;
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
{
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
{
intel_batchbuffer_start_atomic_blt
(
batch
,
24
);
intel_batchbuffer_start_atomic_blt
(
batch
,
24
);
BEGIN_BLT_BATCH
(
batch
,
6
);
BEGIN_BLT_BATCH
(
batch
,
6
);
}
else
{
}
else
{
...
@@ -2115,7 +2116,8 @@ intel_render_put_surface(VADriverContextP ctx,
...
@@ -2115,7 +2116,8 @@ intel_render_put_surface(VADriverContextP ctx,
destx
,
desty
,
destw
,
desth
,
destx
,
desty
,
destw
,
desth
,
flag
);
flag
);
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
gen6_render_put_surface
(
ctx
,
surface
,
gen6_render_put_surface
(
ctx
,
surface
,
srcx
,
srcy
,
srcw
,
srch
,
srcx
,
srcy
,
srcw
,
srch
,
destx
,
desty
,
destw
,
desth
,
destx
,
desty
,
destw
,
desth
,
...
@@ -2141,7 +2143,8 @@ intel_render_put_subpicture(VADriverContextP ctx,
...
@@ -2141,7 +2143,8 @@ intel_render_put_subpicture(VADriverContextP ctx,
{
{
struct
i965_driver_data
*
i965
=
i965_driver_data
(
ctx
);
struct
i965_driver_data
*
i965
=
i965_driver_data
(
ctx
);
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
gen6_render_put_subpicture
(
ctx
,
surface
,
gen6_render_put_subpicture
(
ctx
,
surface
,
srcx
,
srcy
,
srcw
,
srch
,
srcx
,
srcy
,
srcw
,
srch
,
destx
,
desty
,
destw
,
desth
);
destx
,
desty
,
destw
,
desth
);
...
@@ -2164,7 +2167,8 @@ i965_render_init(VADriverContextP ctx)
...
@@ -2164,7 +2167,8 @@ i965_render_init(VADriverContextP ctx)
assert
(
NUM_RENDER_KERNEL
==
(
sizeof
(
render_kernels_gen6
)
/
assert
(
NUM_RENDER_KERNEL
==
(
sizeof
(
render_kernels_gen6
)
/
sizeof
(
render_kernels_gen6
[
0
])));
sizeof
(
render_kernels_gen6
[
0
])));
if
(
IS_GEN6
(
i965
->
intel
.
device_id
))
if
(
IS_GEN6
(
i965
->
intel
.
device_id
)
||
IS_GEN7
(
i965
->
intel
.
device_id
))
memcpy
(
render_state
->
render_kernels
,
render_kernels_gen6
,
sizeof
(
render_state
->
render_kernels
));
memcpy
(
render_state
->
render_kernels
,
render_kernels_gen6
,
sizeof
(
render_state
->
render_kernels
));
else
if
(
IS_IRONLAKE
(
i965
->
intel
.
device_id
))
else
if
(
IS_IRONLAKE
(
i965
->
intel
.
device_id
))
memcpy
(
render_state
->
render_kernels
,
render_kernels_gen5
,
sizeof
(
render_state
->
render_kernels
));
memcpy
(
render_state
->
render_kernels
,
render_kernels_gen5
,
sizeof
(
render_state
->
render_kernels
));
...
...
i965_drv_video/intel_batchbuffer.c
View file @
d934d2bd
...
@@ -161,7 +161,8 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
...
@@ -161,7 +161,8 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
{
{
struct
intel_driver_data
*
intel
=
batch
->
intel
;
struct
intel_driver_data
*
intel
=
batch
->
intel
;
if
(
IS_GEN6
(
intel
->
device_id
))
{
if
(
IS_GEN6
(
intel
->
device_id
)
||
IS_GEN7
(
intel
->
device_id
))
{
if
(
batch
->
flag
==
I915_EXEC_RENDER
)
{
if
(
batch
->
flag
==
I915_EXEC_RENDER
)
{
BEGIN_BATCH
(
batch
,
4
);
BEGIN_BATCH
(
batch
,
4
);
OUT_BATCH
(
batch
,
CMD_PIPE_CONTROL
|
0x2
);
OUT_BATCH
(
batch
,
CMD_PIPE_CONTROL
|
0x2
);
...
...
i965_drv_video/intel_driver.h
View file @
d934d2bd
...
@@ -151,6 +151,11 @@ struct intel_region
...
@@ -151,6 +151,11 @@ struct intel_region
#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
/* Server */
#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
/* Server */
#endif
#endif
#define PCI_CHIP_IVYBRIDGE_GT1 0x0152
/* Desktop */
#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
/* Mobile */
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
/* Server */
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_Q45_G || \
...
@@ -171,4 +176,10 @@ struct intel_region
...
@@ -171,4 +176,10 @@ struct intel_region
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S_GT)
devid == PCI_CHIP_SANDYBRIDGE_S_GT)
#define IS_GEN7(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
devid == PCI_CHIP_IVYBRIDGE_GT2 || \
devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
devid == PCI_CHIP_IVYBRIDGE_S_GT1)
#endif
/* _INTEL_DRIVER_H_ */
#endif
/* _INTEL_DRIVER_H_ */
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