Commit bb75774c authored by Xiang, Haihao's avatar Xiang, Haihao

i965_drv_video: clear draw buffer before rendering.

parent 3b220c84
...@@ -1212,11 +1212,53 @@ i965_render_startup(VADriverContextP ctx) ...@@ -1212,11 +1212,53 @@ i965_render_startup(VADriverContextP ctx)
ADVANCE_BATCH(ctx); ADVANCE_BATCH(ctx);
} }
static void
i965_clear_dest_region(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_render_state *render_state = &i965->render_state;
struct intel_region *dest_region = render_state->draw_region;
unsigned int blt_cmd, br13;
int pitch;
blt_cmd = XY_COLOR_BLT_CMD;
br13 = 0xf0 << 16;
pitch = dest_region->pitch;
if (dest_region->cpp == 4) {
br13 |= BR13_8888;
blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
} else {
assert(dest_region->cpp == 2);
br13 |= BR13_565;
}
if (dest_region->tiling != I915_TILING_NONE) {
blt_cmd |= XY_COLOR_BLT_DST_TILED;
pitch /= 4;
}
br13 |= pitch;
BEGIN_BATCH(ctx, 6);
OUT_BATCH(ctx, blt_cmd);
OUT_BATCH(ctx, br13);
OUT_BATCH(ctx, (dest_region->y << 16) | (dest_region->x));
OUT_BATCH(ctx, ((dest_region->y + dest_region->height) << 16) |
(dest_region->x + dest_region->width));
OUT_RELOC(ctx, dest_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH(ctx, 0x0);
ADVANCE_BATCH(ctx);
}
static void static void
i965_surface_render_pipeline_setup(VADriverContextP ctx) i965_surface_render_pipeline_setup(VADriverContextP ctx)
{ {
intel_batchbuffer_start_atomic(ctx, 0x1000); intel_batchbuffer_start_atomic(ctx, 0x1000);
intel_batchbuffer_emit_mi_flush(ctx); intel_batchbuffer_emit_mi_flush(ctx);
i965_clear_dest_region(ctx);
i965_render_pipeline_select(ctx); i965_render_pipeline_select(ctx);
i965_render_state_sip(ctx); i965_render_state_sip(ctx);
i965_render_state_base_address(ctx); i965_render_state_base_address(ctx);
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#define BATCH_RESERVED 0x10 #define BATCH_RESERVED 0x10
#define CMD_MI (0x0 << 29) #define CMD_MI (0x0 << 29)
#define CMD_2D (0x2 << 29)
#define MI_NOOP (CMD_MI | 0) #define MI_NOOP (CMD_MI | 0)
...@@ -29,6 +30,15 @@ ...@@ -29,6 +30,15 @@
#define MI_FLUSH (CMD_MI | (0x4 << 23)) #define MI_FLUSH (CMD_MI | (0x4 << 23))
#define STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0) #define STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
#define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
#define XY_COLOR_BLT_WRITE_RGB (1 << 20)
#define XY_COLOR_BLT_DST_TILED (1 << 11)
/* BR13 */
#define BR13_565 (0x1 << 24)
#define BR13_8888 (0x3 << 24)
struct intel_batchbuffer; struct intel_batchbuffer;
#define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1)) #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
......
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