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Commit 8af77b87 authored by Xiang, Haihao's avatar Xiang, Haihao
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i965_drv_video: [H.264] add support for ILDB

parent 0c70b6b6
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Showing with 6233 additions and 552 deletions
i965_drv_video/Makefile.am
View file @ 8af77b87
......@@ -41,7 +41,8 @@ i965_drv_video_la_SOURCES = \
i965_render.c \
i965_drv_video.c \
i965_avc_bsd.c \
i965_avc_hw_scoreboard.c
i965_avc_hw_scoreboard.c\
i965_avc_ildb.c
noinst_HEADERS = \
object_heap.h \
......@@ -57,4 +58,5 @@ noinst_HEADERS = \
i965_defines.h \
i965_structs.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h
i965_drv_video/i965_avc_bsd.c
View file @ 8af77b87
......@@ -934,6 +934,9 @@ i965_avc_bsd_frame_store_index(VADriverContextP ctx,
void
i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
int i, j;
VAPictureParameterBufferH264 *pic_param;
VASliceParameterBufferH264 *slice_param;
......@@ -946,6 +949,7 @@ i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state)
i965_avc_bsd_img_state(ctx, decode_state);
i965_avc_bsd_qm_state(ctx, decode_state);
i965_h264_context->enable_avc_ildb = 0;
for (j = 0; j < decode_state->num_slice_params; j++) {
assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
......@@ -964,6 +968,10 @@ i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state)
i965_avc_bsd_slice_state(ctx, pic_param, slice_param);
i965_avc_bsd_buf_base_state(ctx, pic_param, slice_param);
i965_avc_bsd_object(ctx, decode_state, pic_param, slice_param);
if (slice_param->disable_deblocking_filter_idc != 1)
i965_h264_context->enable_avc_ildb = 1;
slice_param++;
}
......
i965_drv_video/i965_avc_hw_scoreboard.c
View file @ 8af77b87
......@@ -52,8 +52,8 @@ enum {
};
static unsigned long avc_hw_scoreboard_kernel_offset[] = {
SETHWSCOREBOARD_IP_GEN5,
SETHWSCOREBOARD_MBAFF_IP_GEN5
SETHWSCOREBOARD_IP_GEN5 * INST_UNIT_GEN5,
SETHWSCOREBOARD_MBAFF_IP_GEN5 * INST_UNIT_GEN5
};
static unsigned int avc_hw_scoreboard_constants[] = {
......@@ -301,11 +301,9 @@ i965_avc_hw_scoreboard(VADriverContextP ctx, struct decode_state *decode_state)
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context;
if (i965_h264_context->use_avc_hw_scoreboard) {
assert(i965_h264_context != NULL);
avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
avc_hw_scoreboard_context->inline_data.num_mb_cmds = i965_h264_context->avc_it_command_mb_info.mbs;
avc_hw_scoreboard_context->inline_data.starting_mb_number = i965_h264_context->avc_it_command_mb_info.mbs;
......@@ -333,12 +331,10 @@ i965_avc_hw_scoreboard_decode_init(VADriverContextP ctx)
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context;
dri_bo *bo;
if (i965_h264_context->use_avc_hw_scoreboard) {
assert(i965_h264_context != NULL);
avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
dri_bo *bo;
dri_bo_unreference(avc_hw_scoreboard_context->curbe.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
......
i965_drv_video/i965_avc_ildb.c 0 → 100644
View file @ 8af77b87
/*
* Copyright © 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Xiang Haihao <haihao.xiang@intel.com>
*
*/
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include "va_backend.h"
#include "intel_batchbuffer.h"
#include "intel_driver.h"
#include "i965_defines.h"
#include "i965_drv_video.h"
#include "i965_avc_ildb.h"
#include "i965_media_h264.h"
#include "i965_media.h"
/* On Cantiga */
#include "shaders/h264/mc/export.inc"
/* On Ironlake */
#include "shaders/h264/mc/export.inc.gen5"
#define PICTURE_FRAME 0
#define PICTURE_FIELD 1
#define PICTURE_MBAFF 2
enum {
AVC_ILDB_ROOT_Y_ILDB_FRAME,
AVC_ILDB_CHILD_Y_ILDB_FRAME,
AVC_ILDB_ROOT_UV_ILDB_FRAME,
AVC_ILDB_CHILD_UV_ILDB_FRAME,
AVC_ILDB_ROOT_Y_ILDB_FIELD,
AVC_ILDB_CHILD_Y_ILDB_FIELD,
AVC_ILDB_ROOT_UV_ILDB_FIELD,
AVC_ILDB_CHILD_UV_ILDB_FIELD,
AVC_ILDB_ROOT_Y_ILDB_MBAFF,
AVC_ILDB_CHILD_Y_ILDB_MBAFF,
AVC_ILDB_ROOT_UV_ILDB_MBAFF,
AVC_ILDB_CHILD_UV_ILDB_MBAFF
};
static unsigned long avc_ildb_kernel_offset_gen4[] = {
AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4,
AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4
};
static unsigned long avc_ildb_kernel_offset_gen5[] = {
AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5
};
struct avc_ildb_root_input
{
unsigned int blocks_per_row : 16;
unsigned int blocks_per_column : 16;
unsigned int picture_type : 16;
unsigned int max_concurrent_threads : 16;
unsigned int debug_field : 16;
unsigned int mbaff_frame_flag : 1;
unsigned int bottom_field_flag : 1;
unsigned int control_data_expansion_flag : 1;
unsigned int chroma_format : 1;
unsigned int pad0 : 12;
unsigned int ramp_constant_0;
unsigned int ramp_constant_1;
int constant_0 : 8;
int constant_1 : 8;
int pad1 : 16;
unsigned int pad2;
unsigned int pad3;
};
extern struct media_kernel *h264_avc_kernels;
#define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
static unsigned long *avc_ildb_kernel_offset = NULL;
static void
i965_avc_ildb_surface_state(VADriverContextP ctx, struct decode_state *decode_state)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
struct i965_surface_state *ss;
struct object_surface *obj_surface;
VAPictureParameterBufferH264 *pic_param;
VAPictureH264 *va_pic;
dri_bo *bo;
int i;
assert(decode_state->pic_param && decode_state->pic_param->buffer);
pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
va_pic = &pic_param->CurrPic;
assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
obj_surface = SURFACE(va_pic->picture_id);
assert(obj_surface);
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo;
dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo);
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0;
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER;
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f);
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff);
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f);
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1;
avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0;
avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo;
dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo);
avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0;
avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D;
avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT;
avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1;
avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1;
avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0;
avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1;
avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0;
avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo;
dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo);
avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height;
avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D;
avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1;
avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1;
avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0;
avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1;
avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0;
avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo;
dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo);
avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0;
avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D;
avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT;
avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1;
avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1;
avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0;
avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1;
avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1;
avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo;
dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo);
avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height;
avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D;
avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1;
avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1;
avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0;
avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1;
avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1;
for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
bo = avc_ildb_context->surface[i].ss_bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
ss = bo->virtual;
memset(ss, 0, sizeof(*ss));
ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type;
ss->ss0.surface_format = avc_ildb_context->surface[i].format;
ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride;
ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs;
ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset;
ss->ss2.width = avc_ildb_context->surface[i].width;
ss->ss2.height = avc_ildb_context->surface[i].height;
ss->ss3.depth = avc_ildb_context->surface[i].depth;
ss->ss3.pitch = avc_ildb_context->surface[i].pitch;
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_RENDER,
avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0,
avc_ildb_context->surface[i].offset,
offsetof(struct i965_surface_state, ss1),
avc_ildb_context->surface[i].s_bo);
dri_bo_unmap(bo);
}
}
static void
i965_avc_ildb_binding_table(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
unsigned int *binding_table;
dri_bo *bo = avc_ildb_context->binding_table.bo;
int i;
dri_bo_map(bo, 1);
assert(bo->virtual);
binding_table = bo->virtual;
memset(binding_table, 0, bo->size);
for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset;
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
i * sizeof(*binding_table),
avc_ildb_context->surface[i].ss_bo);
}
dri_bo_unmap(bo);
}
static void
i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
struct i965_interface_descriptor *desc;
dri_bo *bo;
int i;
bo = avc_ildb_context->idrt.bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
desc = bo->virtual;
for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) {
int kernel_offset = avc_ildb_kernel_offset[i];
memset(desc, 0, sizeof(*desc));
desc->desc0.grf_reg_blocks = 9;
desc->desc0.kernel_start_pointer = (h264_avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
desc->desc1.const_urb_entry_read_offset = 0;
desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0);
desc->desc3.binding_table_entry_count = 0;
desc->desc3.binding_table_pointer =
avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc0.grf_reg_blocks + kernel_offset,
i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
h264_avc_kernels[H264_AVC_COMBINED].bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc3.binding_table_entry_count,
i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
avc_ildb_context->binding_table.bo);
desc++;
}
dri_bo_unmap(bo);
}
static void
i965_avc_ildb_vfe_state(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
struct i965_vfe_state *vfe_state;
dri_bo *bo;
bo = avc_ildb_context->vfe_state.bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
vfe_state = bo->virtual;
memset(vfe_state, 0, sizeof(*vfe_state));
vfe_state->vfe1.max_threads = 0;
vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1;
vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries;
vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
vfe_state->vfe1.children_present = 1;
vfe_state->vfe2.interface_descriptor_base =
avc_ildb_context->idrt.bo->offset >> 4; /* reloc */
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
offsetof(struct i965_vfe_state, vfe2),
avc_ildb_context->idrt.bo);
dri_bo_unmap(bo);
}
static void
i965_avc_ildb_upload_constants(VADriverContextP ctx, struct decode_state *decode_state)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
VAPictureParameterBufferH264 *pic_param;
struct avc_ildb_root_input *root_input;
assert(decode_state->pic_param && decode_state->pic_param->buffer);
pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
dri_bo_map(avc_ildb_context->curbe.bo, 1);
assert(avc_ildb_context->curbe.bo->virtual);
root_input = avc_ildb_context->curbe.bo->virtual;
root_input->max_concurrent_threads = 36; /* FIXME: ??? */
if (pic_param->pic_fields.bits.field_pic_flag)
root_input->picture_type = PICTURE_FIELD;
else {
if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag)
root_input->picture_type = PICTURE_MBAFF;
else
root_input->picture_type = PICTURE_FRAME;
}
avc_ildb_context->picture_type = root_input->picture_type;
root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1;
root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) /
(1 + (root_input->picture_type != PICTURE_FRAME));
avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) *
(pic_param->picture_height_in_mbs_minus1 + 1);
root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF);
root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD);
root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */
root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */
root_input->ramp_constant_0 = 0x03020100;
root_input->ramp_constant_1 = 0x07060504;
root_input->constant_0 = -2;
root_input->constant_1 = 1;
dri_bo_unmap(avc_ildb_context->curbe.bo);
}
static void
i965_avc_ildb_states_setup(VADriverContextP ctx, struct decode_state *decode_state)
{
i965_avc_ildb_surface_state(ctx, decode_state);
i965_avc_ildb_binding_table(ctx);
i965_avc_ildb_interface_descriptor_table(ctx);
i965_avc_ildb_vfe_state(ctx);
i965_avc_ildb_upload_constants(ctx, decode_state);
}
static void
i965_avc_ildb_pipeline_select(VADriverContextP ctx)
{
BEGIN_BATCH(ctx, 1);
OUT_BATCH(ctx, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_urb_layout(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
unsigned int vfe_fence, cs_fence;
vfe_fence = avc_ildb_context->urb.cs_start;
cs_fence = URB_SIZE((&i965->intel));
BEGIN_BATCH(ctx, 3);
OUT_BATCH(ctx, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
OUT_BATCH(ctx, 0);
OUT_BATCH(ctx,
(vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
(cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_state_base_address(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
if (IS_IRONLAKE(i965->intel.device_id)) {
BEGIN_BATCH(ctx, 8);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
} else {
BEGIN_BATCH(ctx, 6);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
}
}
static void
i965_avc_ildb_state_pointers(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
BEGIN_BATCH(ctx, 3);
OUT_BATCH(ctx, CMD_MEDIA_STATE_POINTERS | 1);
OUT_BATCH(ctx, 0);
OUT_RELOC(ctx, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_cs_urb_layout(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
BEGIN_BATCH(ctx, 2);
OUT_BATCH(ctx, CMD_CS_URB_STATE | 0);
OUT_BATCH(ctx,
((avc_ildb_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
(avc_ildb_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_constant_buffer(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
BEGIN_BATCH(ctx, 2);
OUT_BATCH(ctx, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
OUT_RELOC(ctx, avc_ildb_context->curbe.bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
avc_ildb_context->urb.size_cs_entry - 1);
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_objects(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
BEGIN_BATCH(ctx, 4);
OUT_BATCH(ctx, CMD_MEDIA_OBJECT | 4);
switch (avc_ildb_context->picture_type) {
case PICTURE_FRAME:
OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_FRAME);
break;
case PICTURE_FIELD:
OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_FIELD);
break;
case PICTURE_MBAFF:
OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_MBAFF);
break;
default:
assert(0);
OUT_BATCH(ctx, 0);
break;
}
OUT_BATCH(ctx, 0); /* no indirect data */
OUT_BATCH(ctx, 0);
OUT_BATCH(ctx, 0);
OUT_BATCH(ctx, 0);
ADVANCE_BATCH(ctx);
}
static void
i965_avc_ildb_pipeline_setup(VADriverContextP ctx)
{
intel_batchbuffer_emit_mi_flush(ctx);
i965_avc_ildb_pipeline_select(ctx);
i965_avc_ildb_state_base_address(ctx);
i965_avc_ildb_state_pointers(ctx);
i965_avc_ildb_urb_layout(ctx);
i965_avc_ildb_cs_urb_layout(ctx);
i965_avc_ildb_constant_buffer(ctx);
i965_avc_ildb_objects(ctx);
}
void
i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
if (i965_h264_context->enable_avc_ildb) {
intel_batchbuffer_end_atomic(ctx);
intel_batchbuffer_flush(ctx);
intel_batchbuffer_start_atomic(ctx, 0x1000);
i965_avc_ildb_states_setup(ctx, decode_state);
i965_avc_ildb_pipeline_setup(ctx);
}
}
void
i965_avc_ildb_decode_init(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_media_state *media_state = &i965->media_state;
struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_state->private_context;
struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;;
dri_bo *bo;
int i;
dri_bo_unreference(avc_ildb_context->curbe.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"constant buffer",
4096, 64);
assert(bo);
avc_ildb_context->curbe.bo = bo;
dri_bo_unreference(avc_ildb_context->binding_table.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"binding table",
NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32);
assert(bo);
avc_ildb_context->binding_table.bo = bo;
dri_bo_unreference(avc_ildb_context->idrt.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"interface discriptor",
NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16);
assert(bo);
avc_ildb_context->idrt.bo = bo;
dri_bo_unreference(avc_ildb_context->vfe_state.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"vfe state",
sizeof(struct i965_vfe_state), 32);
assert(bo);
avc_ildb_context->vfe_state.bo = bo;
avc_ildb_context->urb.num_vfe_entries = 1;
avc_ildb_context->urb.size_vfe_entry = 640;
avc_ildb_context->urb.num_cs_entries = 1;
avc_ildb_context->urb.size_cs_entry = 1;
avc_ildb_context->urb.vfe_start = 0;
avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start +
avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry;
assert(avc_ildb_context->urb.cs_start +
avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
avc_ildb_context->surface[i].s_bo = NULL;
dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"surface state",
sizeof(struct i965_surface_state), 32);
assert(bo);
avc_ildb_context->surface[i].ss_bo = bo;
}
/* kernel offset */
assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5));
if (IS_IRONLAKE(i965->intel.device_id)) {
avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5;
} else {
avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4;
}
}
Bool
i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context)
{
int i;
dri_bo_unreference(avc_ildb_context->curbe.bo);
avc_ildb_context->curbe.bo = NULL;
dri_bo_unreference(avc_ildb_context->binding_table.bo);
avc_ildb_context->binding_table.bo = NULL;
dri_bo_unreference(avc_ildb_context->idrt.bo);
avc_ildb_context->idrt.bo = NULL;
dri_bo_unreference(avc_ildb_context->vfe_state.bo);
avc_ildb_context->vfe_state.bo = NULL;
for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
avc_ildb_context->surface[i].ss_bo = NULL;
dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
avc_ildb_context->surface[i].s_bo = NULL;
}
return True;
}
i965_drv_video/i965_avc_ildb.h 0 → 100644
View file @ 8af77b87
/*
* Copyright © 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Xiang Haihao <haihao.xiang@intel.com>
*
*/
#ifndef __I965_AVC_ILDB_H__
#define __I965_AVC_ILDB_H__
#define SURFACE_EDGE_CONTROL_DATA 0
#define SURFACE_SRC_Y 1
#define SURFACE_SRC_UV 2
#define SURFACE_DEST_Y 3
#define SURFACE_DEST_UV 4
#define NUM_AVC_ILDB_SURFACES 5
#define EDGE_CONTROL_DATA_IN_DWS 16
#define EDGE_CONTROL_DATA_IN_BTYES 64
struct i965_avc_ildb_context
{
struct {
dri_bo *bo;
} curbe;
struct {
dri_bo *ss_bo;
dri_bo *s_bo;
unsigned long offset;
int surface_type;
int width;
int height;
int depth;
int pitch;
int format;
int vert_line_stride;
int vert_line_stride_ofs;
int is_target;
} surface[NUM_AVC_ILDB_SURFACES];
struct {
dri_bo *bo;
} binding_table;
struct {
dri_bo *bo;
} idrt;
struct {
dri_bo *bo;
} vfe_state;
struct {
unsigned int vfe_start;
unsigned int cs_start;
unsigned int num_vfe_entries;
unsigned int num_cs_entries;
unsigned int size_vfe_entry;
unsigned int size_cs_entry;
} urb;
int picture_type;
int mbs_per_picture;
};
void i965_avc_ildb(VADriverContextP, struct decode_state *);
void i965_avc_ildb_decode_init(VADriverContextP);
Bool i965_avc_ildb_ternimate(struct i965_avc_ildb_context *);
#endif /* __I965_AVC_ILDB_H__ */
i965_drv_video/i965_media_h264.c
View file @ 8af77b87
......@@ -88,54 +88,53 @@ struct inter_kernel_header
#include "shaders/h264/mc/export.inc"
static unsigned long avc_mc_kernel_offset_gen4[] = {
INTRA_16x16_IP,
INTRA_8x8_IP,
INTRA_4x4_IP,
INTRA_PCM_IP,
FRAME_MB_IP,
FIELD_MB_IP,
MBAFF_MB_IP
INTRA_16x16_IP * INST_UNIT_GEN4,
INTRA_8x8_IP * INST_UNIT_GEN4,
INTRA_4x4_IP * INST_UNIT_GEN4,
INTRA_PCM_IP * INST_UNIT_GEN4,
FRAME_MB_IP * INST_UNIT_GEN4,
FIELD_MB_IP * INST_UNIT_GEN4,
MBAFF_MB_IP * INST_UNIT_GEN4
};
#define INST_UNIT_GEN4 16
struct intra_kernel_header intra_kernel_header_gen4 = {
0 / INST_UNIT_GEN4,
(INTRA_4X4_HORIZONTAL_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_DC_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_DIAG_DOWN_LEFT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
0,
(INTRA_4X4_HORIZONTAL_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_DC_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_DIAG_DOWN_LEFT_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_DIAG_DOWN_RIGHT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_VERT_RIGHT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_HOR_DOWN_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_VERT_LEFT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_DIAG_DOWN_RIGHT_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_VERT_RIGHT_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_HOR_DOWN_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_VERT_LEFT_IP - INTRA_4X4_VERTICAL_IP),
(INTRA_4X4_HOR_UP_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_4X4_HOR_UP_IP - INTRA_4X4_VERTICAL_IP),
0,
0xFFFC,
0 / INST_UNIT_GEN4,
(INTRA_8X8_HORIZONTAL_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_DC_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_DIAG_DOWN_LEFT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
0,
(INTRA_8X8_HORIZONTAL_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_DC_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_DIAG_DOWN_LEFT_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_DIAG_DOWN_RIGHT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_VERT_RIGHT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_HOR_DOWN_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_VERT_LEFT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_DIAG_DOWN_RIGHT_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_VERT_RIGHT_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_HOR_DOWN_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_VERT_LEFT_IP - INTRA_8X8_VERTICAL_IP),
(INTRA_8X8_HOR_UP_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_8X8_HOR_UP_IP - INTRA_8X8_VERTICAL_IP),
0,
0x0001,
0 / INST_UNIT_GEN4,
(INTRA_16x16_HORIZONTAL_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_16x16_DC_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
(INTRA_16x16_PLANE_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
0,
(INTRA_16x16_HORIZONTAL_IP - INTRA_16x16_VERTICAL_IP),
(INTRA_16x16_DC_IP - INTRA_16x16_VERTICAL_IP),
(INTRA_16x16_PLANE_IP - INTRA_16x16_VERTICAL_IP),
0 / INST_UNIT_GEN4,
(INTRA_CHROMA_HORIZONTAL_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
(INTRA_CHROMA_VERTICAL_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
(INTRA_Chroma_PLANE_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
0,
(INTRA_CHROMA_HORIZONTAL_IP - INTRA_CHROMA_DC_IP),
(INTRA_CHROMA_VERTICAL_IP - INTRA_CHROMA_DC_IP),
(INTRA_Chroma_PLANE_IP - INTRA_CHROMA_DC_IP),
0xFCFBFAF9,
......@@ -149,10 +148,10 @@ struct intra_kernel_header intra_kernel_header_gen4 = {
0x00020406,
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB3_IP) / INST_UNIT_GEN4 * 0x1000000 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB2_IP) / INST_UNIT_GEN4 * 0x10000 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB1_IP) / INST_UNIT_GEN4 * 0x100 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB0_IP) / INST_UNIT_GEN4
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB3_IP) * 0x1000000 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB2_IP) * 0x10000 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB1_IP) * 0x100 +
(intra_Pred_4x4_Y_IP - ADD_ERROR_SB0_IP)
};
static uint32_t h264_avc_combined_gen4[][4] = {
......@@ -184,55 +183,53 @@ static struct media_kernel h264_avc_kernels_gen4[] = {
/* On Ironlake */
#include "shaders/h264/mc/export.inc.gen5"
static unsigned long avc_mc_kernel_offset_gen5[] = {
INTRA_16x16_IP_GEN5,
INTRA_8x8_IP_GEN5,
INTRA_4x4_IP_GEN5,
INTRA_PCM_IP_GEN5,
FRAME_MB_IP_GEN5,
FIELD_MB_IP_GEN5,
MBAFF_MB_IP_GEN5
INTRA_16x16_IP_GEN5 * INST_UNIT_GEN5,
INTRA_8x8_IP_GEN5 * INST_UNIT_GEN5,
INTRA_4x4_IP_GEN5 * INST_UNIT_GEN5,
INTRA_PCM_IP_GEN5 * INST_UNIT_GEN5,
FRAME_MB_IP_GEN5 * INST_UNIT_GEN5,
FIELD_MB_IP_GEN5 * INST_UNIT_GEN5,
MBAFF_MB_IP_GEN5 * INST_UNIT_GEN5
};
#define INST_UNIT_GEN5 8
struct intra_kernel_header intra_kernel_header_gen5 = {
0 / INST_UNIT_GEN5,
(INTRA_4X4_HORIZONTAL_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_DC_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
0,
(INTRA_4X4_HORIZONTAL_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_DC_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_VERT_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_HOR_DOWN_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_VERT_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_VERT_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_HOR_DOWN_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_VERT_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
(INTRA_4X4_HOR_UP_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_4X4_HOR_UP_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
0,
0xFFFC,
0 / INST_UNIT_GEN5,
(INTRA_8X8_HORIZONTAL_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_DC_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
0,
(INTRA_8X8_HORIZONTAL_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_DC_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_VERT_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_HOR_DOWN_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_VERT_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_VERT_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_HOR_DOWN_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_VERT_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
(INTRA_8X8_HOR_UP_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_8X8_HOR_UP_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
0,
0x0001,
0 / INST_UNIT_GEN5,
(INTRA_16x16_HORIZONTAL_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_16x16_DC_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_16x16_PLANE_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
0,
(INTRA_16x16_HORIZONTAL_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
(INTRA_16x16_DC_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
(INTRA_16x16_PLANE_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
0 / INST_UNIT_GEN5,
(INTRA_CHROMA_HORIZONTAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_CHROMA_VERTICAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
(INTRA_Chroma_PLANE_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
0,
(INTRA_CHROMA_HORIZONTAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
(INTRA_CHROMA_VERTICAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
(INTRA_Chroma_PLANE_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
0xFCFBFAF9,
......@@ -246,10 +243,10 @@ struct intra_kernel_header intra_kernel_header_gen5 = {
0x00020406,
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB3_IP_GEN5) / INST_UNIT_GEN5 * 0x1000000 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB2_IP_GEN5) / INST_UNIT_GEN5 * 0x10000 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB1_IP_GEN5) / INST_UNIT_GEN5 * 0x100 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB0_IP_GEN5) / INST_UNIT_GEN5
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB3_IP_GEN5) * 0x1000000 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB2_IP_GEN5) * 0x10000 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB1_IP_GEN5) * 0x100 +
(intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB0_IP_GEN5)
};
static uint32_t h264_avc_combined_gen5[][4] = {
......@@ -758,6 +755,8 @@ i965_media_h264_objects(VADriverContextP ctx, struct decode_state *decode_state)
I915_GEM_DOMAIN_COMMAND, 0,
0);
ADVANCE_BATCH(ctx);
i965_avc_ildb(ctx, decode_state);
}
void
......@@ -806,6 +805,9 @@ i965_media_h264_decode_init(VADriverContextP ctx)
/* HW scoreboard */
i965_avc_hw_scoreboard_decode_init(ctx);
/* ILDB */
i965_avc_ildb_decode_init(ctx);
/* for Media pipeline */
media_state->extended_state.enabled = 1;
dri_bo_unreference(media_state->extended_state.bo);
......@@ -882,6 +884,7 @@ i965_media_h264_init(VADriverContextP ctx)
i965_h264_context->fsid_list[i].frame_store_id = -1;
}
i965_h264_context->enable_avc_ildb = 0;
media_state->private_context = i965_h264_context;
return True;
}
......@@ -896,6 +899,7 @@ i965_media_h264_ternimate(VADriverContextP ctx)
if (media_state->private_context) {
i965_h264_context = (struct i965_h264_context *)media_state->private_context;
i965_avc_ildb_ternimate(&i965_h264_context->avc_ildb_context);
i965_avc_hw_scoreboard_ternimate(&i965_h264_context->avc_hw_scoreboard_context);
i965_avc_bsd_ternimate(&i965_h264_context->i965_avc_bsd_context);
dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
......
i965_drv_video/i965_media_h264.h
View file @ 8af77b87
......@@ -3,6 +3,10 @@
#include "i965_avc_bsd.h"
#include "i965_avc_hw_scoreboard.h"
#include "i965_avc_ildb.h"
#define INST_UNIT_GEN4 16
#define INST_UNIT_GEN5 8
#define MB_CMD_IN_BYTES 64
#define MB_CMD_IN_DWS 16
......@@ -35,6 +39,7 @@ struct i965_h264_context
int mbaff_frame_flag;
} picture;
int enable_avc_ildb;
int use_avc_hw_scoreboard;
int use_hw_w128;
......@@ -47,6 +52,8 @@ struct i965_h264_context
struct i965_avc_bsd_context i965_avc_bsd_context;
struct i965_avc_hw_scoreboard_context avc_hw_scoreboard_context;
struct i965_avc_ildb_context avc_ildb_context;
struct {
VASurfaceID surface_id;
int frame_store_id;
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB.inc
View file @ 8af77b87
......@@ -239,7 +239,7 @@
#define FilterSampleFlag r28.0 // :uw,
.declare A Base=r28.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w
.declare B Base=r29.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w
.declare BB Base=r29.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w
.declare TempRow3 Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
.declare TempRow3B Base=r30.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_Mbaff_UV.asm
View file @ 8af77b87
......@@ -23,7 +23,7 @@
ILDB_LABEL(AVC_ILDB_CHILD_UV):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
#if defined(_DEBUG)
......@@ -85,9 +85,9 @@ ILDB_LABEL(RE_ENTRY_UV): // for bootom field
// Load current MB control data
#if defined(DEV_CL)
#include "load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#else
#include "load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#endif
// Init addr register for vertical control data
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_Mbaff_Y.asm
View file @ 8af77b87
......@@ -39,7 +39,7 @@
ILDB_LABEL(AVC_ILDB_CHILD_Y):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
#if defined(_DEBUG)
......@@ -99,9 +99,9 @@ RE_ENTRY: // for bootom field
// Load current MB control data
#if defined(DEV_CL)
#include "load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#else
#include "load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#endif
// Init addr register for vertical control data
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_UV.asm
View file @ 8af77b87
......@@ -23,7 +23,7 @@
ILDB_LABEL(AVC_ILDB_CHILD_UV):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
#if defined(_DEBUG)
......@@ -71,12 +71,12 @@ ILDB_LABEL(AVC_ILDB_CHILD_UV):
// Load current MB control data
#if defined(DEV_CL)
#if defined(_APPLE)
#include "load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only
#include "Load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only
#else
#include "load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#endif
#else
#include "load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#endif
// Check loaded control data
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_Y.asm
View file @ 8af77b87
......@@ -22,7 +22,7 @@
ILDB_LABEL(AVC_ILDB_CHILD_Y):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
#if defined(_DEBUG)
......@@ -58,12 +58,12 @@ ILDB_LABEL(AVC_ILDB_CHILD_Y):
// Load current MB control data
#if defined(DEV_CL)
#if defined(_APPLE)
#include "load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only
#include "Load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only
#else
#include "load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline
#endif
#else
#include "load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond
#endif
// Check loaded control data
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_CloseGateway.asm
View file @ 8af77b87
......@@ -19,4 +19,4 @@
// 19:16 Response length = 0
// 1:0 SubFuncID = 01 for CloseGateway
// Message descriptor: 0 000 0011 0001 0000 + 0 0 000000000000 01 ==> 0000 0011 0001 0000 0000 0000 0000 0001
send (8) null:ud m7 r0.0:ud MSG_GW CGWMSGDSC
send (8) null:ud m7 r0.0<0;1,0>:ud MSG_GW CGWMSGDSC
i965_drv_video/shaders/h264/ildb/AVC_ILDB_LumaThrdLimit.asm
View file @ 8af77b87
......@@ -38,7 +38,7 @@ mov (1) GatewayPayloadKey:uw 0x1212:uw { NoDDChk } // Key
// Write back one byte (value = 0xFF) to root thread GRF to indicate this child thread is finished
// All lower 4 bytes must be assigned to the same byte value.
add (1) Temp1_W:w MaxThreads:uw -OutstandingThreads:uw
mov (4) GatewayPayload<1>:ub Temp1_B:ub
mov (4) GatewayPayload<1>:ub Temp1_B<0;1,0>:ub
send (8) GatewayResponse:ud m0 GatewayPayload<8;8,1>:ud MSG_GW FWDMSGDSC
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Luma_Core.asm
View file @ 8af77b87
......@@ -172,28 +172,28 @@ FILTER_Y:
// B = p2 + (p1 + p0 + q0) + 4 = p2 + A + 4
// add (16) acc0.0<1>:w P2 4:w // p2 + 4
// add (16) B(0)<1> acc0.0<16;16,1>:w A(0) // B = p2 + A + 4
// add (16) BB(0)<1> acc0.0<16;16,1>:w A(0) // B = p2 + A + 4
add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // p2 + 4
add (16) B(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4
add (16) BB(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4
// Now acc0 = B
// p2' = (2*p3 +3*p2 + A + 4) >> 3 = (2*(p3+p2) + B) >> 3
// mov (16) acc0.0<1>:w B(0)
// mov (16) acc0.0<1>:w BB(0)
mac (16) acc0.0<1>:w P2_plus_P3(0) 2:w
shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w
// p1' = (p2 + A + 2) >> 2 = (B - 2) >> 2
add (16) acc0.0<1>:w B(0) -2:w
add (16) acc0.0<1>:w BB(0) -2:w
shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w
// p0' = (p2 +2*A + q1 + 4) >> 3 = (B + A + q1) >> 3
add (16) acc0.0<1>:w Q1 A(0) // B + A
add (16) acc0.0<1>:w acc0.0<16;16,1>:w B(0) // B + A + q1
add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) // B + A + q1
shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w // (B + A + q1) >> 3
// p2' = (2*p3 +3*p2 + A + 4) >> 3 = (2*(p3+p2) + B) >> 3
// mov (16) acc0.0<1>:w B(0)
// mov (16) acc0.0<1>:w BB(0)
// mac (16) acc0.0<1>:w P2_plus_P3(0) 2:w
// shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w
......@@ -246,22 +246,22 @@ Y_ENDIF3:
// B = q2 + q1 + q0 + p0 + 4 = q2 + A + 4
add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // q2 + 4
add (16) B(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4
add (16) BB(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4
// Acc0 = B
// q2' = (2*q3 +3*q2 + A + 4) >> 3 = (2*(q3+q2) + B) >> 3
// mov (16) acc0.0<1>:w B(0)
// mov (16) acc0.0<1>:w BB(0)
mac (16) acc0.0<1>:w Q2_plus_Q3(0) 2:w
shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w
// q1' = (q2 + A + 2) >> 2 = (B - 2) >> 2
add (16) acc0.0<1>:w B(0) -2:w
add (16) acc0.0<1>:w BB(0) -2:w
shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w
// q0' = (q2 +2*A + p1 + 4) >> 3 = (B + A + p1) >> 3
add (16) acc0.0<1>:w p1(0) A(0)
add (16) acc0.0<1>:w acc0.0<16;16,1>:w B(0)
add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0)
shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w
mov (16) NewQ2 TempRow3B(0) // q2'
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Luma_Core_Mbaff.asm
View file @ 8af77b87
......@@ -170,7 +170,7 @@ FILTER_Y_MBAFF:
// B = p2 + p1 + p0 + q0 + 4 = p2 + A + 4
add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // p2 + 4
add (16) B(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4
add (16) BB(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4
// Now acc0 = B
......@@ -179,12 +179,12 @@ FILTER_Y_MBAFF:
shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w
// p1' = (p2 + A + 2) >> 2 = (B - 2) >> 2
add (16) acc0.0<1>:w B(0) -2:w
add (16) acc0.0<1>:w BB(0) -2:w
shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w
// p0' = (p2 +2*A + q1 + 4) >> 3 = (B + A + q1) >> 3
add (16) acc0.0<1>:w Q1 A(0) // B + A
add (16) acc0.0<1>:w acc0.0<16;16,1>:w B(0) // B + A + q1
add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) // B + A + q1
shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w // (B + A + q1) >> 3
mov (16) NewP2 TempRow3B(0) // p2'
......@@ -227,7 +227,7 @@ MBAFF_Y_ENDIF3:
// B = q2 + q1 + q0 + p0 + 4 = q2 + A + 4
add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // q2 + 4
add (16) B(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4
add (16) BB(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4
// Acc0 = B
......@@ -236,12 +236,12 @@ MBAFF_Y_ENDIF3:
shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w
// q1' = (q2 + A + 2) >> 2 = (B - 2) >> 2
add (16) acc0.0<1>:w B(0) -2:w
add (16) acc0.0<1>:w BB(0) -2:w
shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w
// q0' = (q2 +2*A + p1 + 4) >> 3 = (B + A + p1) >> 3
add (16) acc0.0<1>:w p1(0) A(0)
add (16) acc0.0<1>:w acc0.0<16;16,1>:w B(0)
add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0)
shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w
mov (16) NewQ2 TempRow3B(0) // q2'
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_Mbaff_UV.asm
View file @ 8af77b87
......@@ -35,7 +35,7 @@
ILDB_LABEL(AVC_ILDB_ROOT_UV):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_Mbaff_Y.asm
View file @ 8af77b87
......@@ -35,7 +35,7 @@
ILDB_LABEL(AVC_ILDB_ROOT_Y):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_UV.asm
View file @ 8af77b87
......@@ -24,7 +24,7 @@
ILDB_LABEL(AVC_ILDB_ROOT_UV):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
#if defined(_DEBUG)
......
i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_Y.asm
View file @ 8af77b87
......@@ -24,7 +24,7 @@
ILDB_LABEL(AVC_ILDB_ROOT_Y):
#endif
#include "setupVPKernel.asm"
#include "SetupVPKernel.asm"
#include "AVC_ILDB.inc"
/////////////////////////////////////////////////////////////////////////////////////
......
i965_drv_video/shaders/h264/ildb/ILDB_header.inc
View file @ 8af77b87
......@@ -86,12 +86,12 @@
#define RETURN_REG r62 // Return pointer for all sub-routine calls (type DWORD)
#define CALL(subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud 1+skipInst*INST_SIZE \n\
#define CALL(subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\
jmpi (1) subFunc
#define RETURN mov (1) ip:ud RETURN_REG<0;1,0>:ud // Return to calling module
#define PRED_CALL(flag, subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud 1+skipInst*INST_SIZE \n\
#define PRED_CALL(flag, subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\
(flag) jmpi (1) subFunc
......
i965_drv_video/shaders/h264/ildb/writeURB.asm
View file @ 8af77b87
......@@ -34,5 +34,5 @@ shr (1) MSGSRC.0:uw URBOffset:uw 1:w // divide by 2, because URB entry is count
//mov (1) MSGSRC.1:ud 0:ud // Reset Handle 1
send null:uw m0 MSGSRC:uw URBWRITE URBWriteMsgDesc:ud // URB write
send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE URBWriteMsgDesc:ud // URB write
//send null:ud MRF0 null:ud URBWriteMsgDesc:ud // URB write
i965_drv_video/shaders/h264/ildb/writeURB_UV_Child.asm
View file @ 8af77b87
......@@ -36,4 +36,4 @@ shr (1) MSGSRC.0:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is coun
// Current MB offset is in URBOffset, use it as write origin
// Add 2 to offset to store data be be passed to the right MB
send null:uw m0 MSGSRC:uw URBWRITE MSG_LEN(1)+URBWMSGDSC+0x20 // URB write
send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE MSG_LEN(1)+URBWMSGDSC+0x20 // URB write
i965_drv_video/shaders/h264/ildb/writeURB_Y_Child.asm
View file @ 8af77b87
......@@ -37,4 +37,4 @@ shr (1) MSGSRC.0:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is coun
// Add 2 to offset to store data be be passed to the right MB
//mov (1) URBWriteMsgDesc:ud 0x06300020:ud
send null:uw m0 MSGSRC:uw URBWRITE MSG_LEN(2)+URBWMSGDSC+0x20 // URB write
send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE MSG_LEN(2)+URBWMSGDSC+0x20 // URB write
i965_drv_video/shaders/h264/mc/AllAVC.asm
View file @ 8af77b87
......@@ -24,7 +24,7 @@
// ----------------------------------------------------
#define COMBINED_KERNEL
//#define ENABLE_ILDB
#define ENABLE_ILDB
// WA for *Stim tool issue, should be removed later
......
i965_drv_video/shaders/h264/mc/avc_mc.g4b
View file @ 8af77b87
This source diff could not be displayed because it is too large. You can view the blob instead.
i965_drv_video/shaders/h264/mc/avc_mc.g4b.gen5
View file @ 8af77b87
This source diff could not be displayed because it is too large. You can view the blob instead.
i965_drv_video/shaders/h264/mc/export.inc
View file @ 8af77b87
#define INTRA_16x16_IP 0
#define INTRA_16x16_VERTICAL_IP 112
#define INTRA_16x16_HORIZONTAL_IP 256
#define INTRA_16x16_DC_IP 416
#define INTRA_16x16_PLANE_IP 784
#define End_intra_Pred_16x16_Y_IP 1328
#define End_add_Error_16x16_Y_IP 1632
#define load_Intra_Ref_Y_IP 1760
#define decode_Chroma_Intra_IP 1904
#define INTRA_CHROMA_DC_IP 2080
#define INTRA_CHROMA_HORIZONTAL_IP 2560
#define INTRA_CHROMA_VERTICAL_IP 2656
#define INTRA_Chroma_PLANE_IP 2736
#define End_of_intra_Pred_Chroma_IP 3136
#define save_16x16_Y_IP 3488
#define INTRA_8x8_IP 3712
#define INTRA_8x8_BLK2_IP 4544
#define intra_Pred_8x8_Y_IP 5120
#define INTRA_8X8_VERTICAL_IP 5376
#define INTRA_8X8_HORIZONTAL_IP 5456
#define INTRA_8X8_DC_IP 5536
#define INTRA_8X8_DIAG_DOWN_LEFT_IP 5792
#define INTRA_8X8_DIAG_DOWN_RIGHT_IP 5952
#define INTRA_8X8_VERT_RIGHT_IP 6176
#define INTRA_8X8_HOR_DOWN_IP 6464
#define INTRA_8X8_VERT_LEFT_IP 6736
#define INTRA_8X8_HOR_UP_IP 6896
#define save_8x8_Y_IP 7088
#define INTRA_4x4_IP 7424
#define intra_Pred_4x4_Y_4_IP 8496
#define ADD_ERROR_SB0_IP 8592
#define ADD_ERROR_SB1_IP 8704
#define ADD_ERROR_SB2_IP 8864
#define ADD_ERROR_SB3_IP 8992
#define intra_Pred_4x4_Y_IP 9040
#define INTRA_4X4_VERTICAL_IP 9040
#define INTRA_4X4_HORIZONTAL_IP 9072
#define INTRA_4X4_DC_IP 9104
#define INTRA_4X4_DIAG_DOWN_LEFT_IP 9280
#define INTRA_4X4_DIAG_DOWN_RIGHT_IP 9392
#define INTRA_4X4_VERT_RIGHT_IP 9536
#define INTRA_4X4_HOR_DOWN_IP 9744
#define INTRA_4X4_VERT_LEFT_IP 9968
#define INTRA_4X4_HOR_UP_IP 10080
#define save_4x4_Y_IP 10208
#define INTRA_PCM_IP 10560
#define FRAME_MB_IP 11072
#define INIT_MBPARA_FRM_IP 11120
#define NOT_8x8_MODE_FRM_IP 11408
#define CONVERT_MVS_FRM_IP 11488
#define INIT_ADDRESS_REGS_FRM_IP 11568
#define LOOP_SUBMB_FRM_IP 11632
#define LOOP_DIR_FRM_IP 11680
#define LOADREF_MVXZERO_FRM_IP 12080
#define EXIT_LOADREF_Y_16x13_FRM_IP 12192
#define Interpolate_Y_8x8_Func_FRM_IP 12352
#define Interpolate_Y_8x8_Func2_FRM_IP 12592
#define Interpolate_Y_H_8x8_FRM_IP 13664
#define Interpolate_Y_V_8x8_FRM_IP 14320
#define VFILTER_8x8_FRM_IP 14496
#define Interpolate_Y_I_8x8_FRM_IP 14880
#define Average_8x8_FRM_IP 15040
#define Return_Interpolate_Y_8x8_FRM_IP 15104
#define Exit_Interpolate_Y_8x8_FRM_IP 15120
#define Interpolate_C_4x4_Func_FRM_IP 15120
#define PROCESS4x4_FRM_IP 15424
#define LOOP_SUBMBPT_FRM_IP 15440
#define Interpolate_Y_H_4x4_FRM_IP 16528
#define Interpolate_Y_V_4x4_FRM_IP 16864
#define VFILTER_4x4_FRM_IP 17136
#define Interpolate_Y_I_4x4_FRM_IP 17184
#define Average_4x4_FRM_IP 17280
#define Return_Interpolate_Y_4x4_FRM_IP 17296
#define Exit_Interpolate_Y_4x4_FRM_IP 17392
#define ROUND_SHIFT_C_FRM_IP 17776
#define LOOP_DIR_CONTINUE_FRM_IP 17840
#define Weighted_Prediction_FRM_IP 17888
#define DefaultWeightedPred_UniPred_FRM_IP 17952
#define DefaultWeightedPred_BiPred_FRM_IP 18048
#define WeightedPred_FRM_IP 18112
#define WeightedPred_Explicit_FRM_IP 18256
#define WeightedPred_LOOP_FRM_IP 18576
#define Return_WeightedPred_FRM_IP 19056
#define EXIT_LOOP_FRM_IP 19392
#define FIELD_MB_IP 19968
#define INIT_MBPARA_FLD_IP 20016
#define NOT_8x8_MODE_FLD_IP 20304
#define CONVERT_MVS_FLD_IP 20384
#define INIT_ADDRESS_REGS_FLD_IP 20464
#define LOOP_SUBMB_FLD_IP 20544
#define LOOP_DIR_FLD_IP 20592
#define LOADREF_MVXZERO_FLD_IP 21152
#define EXIT_LOADREF_Y_16x13_FLD_IP 21264
#define Interpolate_Y_8x8_Func_FLD_IP 21440
#define Interpolate_Y_8x8_Func2_FLD_IP 21680
#define Interpolate_Y_H_8x8_FLD_IP 22752
#define Interpolate_Y_V_8x8_FLD_IP 23408
#define VFILTER_8x8_FLD_IP 23584
#define Interpolate_Y_I_8x8_FLD_IP 23968
#define Average_8x8_FLD_IP 24128
#define Return_Interpolate_Y_8x8_FLD_IP 24192
#define Exit_Interpolate_Y_8x8_FLD_IP 24208
#define Interpolate_C_4x4_Func_FLD_IP 24208
#define PROCESS4x4_FLD_IP 24512
#define LOOP_SUBMBPT_FLD_IP 24528
#define Interpolate_Y_H_4x4_FLD_IP 25632
#define Interpolate_Y_V_4x4_FLD_IP 25968
#define VFILTER_4x4_FLD_IP 26240
#define Interpolate_Y_I_4x4_FLD_IP 26288
#define Average_4x4_FLD_IP 26384
#define Return_Interpolate_Y_4x4_FLD_IP 26400
#define Exit_Interpolate_Y_4x4_FLD_IP 26496
#define ROUND_SHIFT_C_FLD_IP 26880
#define LOOP_DIR_CONTINUE_FLD_IP 26944
#define Weighted_Prediction_FLD_IP 26992
#define DefaultWeightedPred_UniPred_FLD_IP 27056
#define DefaultWeightedPred_BiPred_FLD_IP 27152
#define WeightedPred_FLD_IP 27216
#define WeightedPred_Explicit_FLD_IP 27360
#define WeightedPred_LOOP_FLD_IP 27680
#define Return_WeightedPred_FLD_IP 28160
#define EXIT_LOOP_FLD_IP 28496
#define MBAFF_MB_IP 29120
#define INIT_MBPARA_MBF_IP 29168
#define NOT_8x8_MODE_MBF_IP 29456
#define CONVERT_MVS_MBF_IP 29536
#define INIT_ADDRESS_REGS_MBF_IP 29616
#define LOOP_SUBMB_MBF_IP 29728
#define LOOP_DIR_MBF_IP 29776
#define LOADREF_MVXZERO_MBF_IP 30368
#define EXIT_LOADREF_Y_16x13_MBF_IP 30480
#define Interpolate_Y_8x8_Func_MBF_IP 30656
#define Interpolate_Y_8x8_Func2_MBF_IP 30896
#define Interpolate_Y_H_8x8_MBF_IP 31968
#define Interpolate_Y_V_8x8_MBF_IP 32624
#define VFILTER_8x8_MBF_IP 32800
#define Interpolate_Y_I_8x8_MBF_IP 33184
#define Average_8x8_MBF_IP 33344
#define Return_Interpolate_Y_8x8_MBF_IP 33408
#define Exit_Interpolate_Y_8x8_MBF_IP 33424
#define Interpolate_C_4x4_Func_MBF_IP 33424
#define PROCESS4x4_MBF_IP 33728
#define LOOP_SUBMBPT_MBF_IP 33744
#define Interpolate_Y_H_4x4_MBF_IP 34848
#define Interpolate_Y_V_4x4_MBF_IP 35184
#define VFILTER_4x4_MBF_IP 35456
#define Interpolate_Y_I_4x4_MBF_IP 35504
#define Average_4x4_MBF_IP 35600
#define Return_Interpolate_Y_4x4_MBF_IP 35616
#define Exit_Interpolate_Y_4x4_MBF_IP 35712
#define ROUND_SHIFT_C_MBF_IP 36096
#define LOOP_DIR_CONTINUE_MBF_IP 36160
#define Weighted_Prediction_MBF_IP 36208
#define DefaultWeightedPred_UniPred_MBF_IP 36272
#define DefaultWeightedPred_BiPred_MBF_IP 36368
#define WeightedPred_MBF_IP 36432
#define WeightedPred_Explicit_MBF_IP 36576
#define WeightedPred_LOOP_MBF_IP 36896
#define Return_WeightedPred_MBF_IP 37376
#define EXIT_LOOP_MBF_IP 37712
#define SETHWSCOREBOARD_IP 38336
#define SetHWScoreboard_Loop_IP 38448
#define Parse_8_Loop_0_IP 38816
#define Parse_8_Loop_2_IP 39008
#define Parse_8_Loop_4_IP 39200
#define Parse_8_Loop_6_IP 39392
#define Parse_8_Loop_8_IP 39584
#define Parse_8_Loop_10_IP 39776
#define Parse_8_Loop_12_IP 39968
#define Parse_8_Loop_14_IP 40160
#define SetHWScoreboard_Remainder_IP 40496
#define SetHWScoreboard_Remainder_Loop_IP 40720
#define Output_Remainder_Intra_IP 40928
#define SetHWScoreboard_Done_IP 41024
#define SETHWSCOREBOARD_MBAFF_IP 41088
#define SetHWScoreboard_MBAFF_Loop_IP 41184
#define SET_SB_MBAFF_INTRA_0_IP 41664
#define SET_SB_MBAFF_0_IP 41840
#define NEXT_MB_MBAFF_0_IP 41904
#define SET_SB_MBAFF_INTRA_2_IP 42208
#define SET_SB_MBAFF_2_IP 42384
#define NEXT_MB_MBAFF_2_IP 42448
#define SET_SB_MBAFF_INTRA_4_IP 42752
#define SET_SB_MBAFF_4_IP 42928
#define NEXT_MB_MBAFF_4_IP 42992
#define SET_SB_MBAFF_INTRA_6_IP 43296
#define SET_SB_MBAFF_6_IP 43472
#define NEXT_MB_MBAFF_6_IP 43536
#define SET_SB_MBAFF_INTRA_8_IP 43840
#define SET_SB_MBAFF_8_IP 44016
#define NEXT_MB_MBAFF_8_IP 44080
#define SET_SB_MBAFF_INTRA_10_IP 44384
#define SET_SB_MBAFF_10_IP 44560
#define NEXT_MB_MBAFF_10_IP 44624
#define SET_SB_MBAFF_INTRA_12_IP 44928
#define SET_SB_MBAFF_12_IP 45104
#define NEXT_MB_MBAFF_12_IP 45168
#define SET_SB_MBAFF_INTRA_14_IP 45472
#define SET_SB_MBAFF_14_IP 45648
#define NEXT_MB_MBAFF_14_IP 45712
#define SetHWScoreboard_MBAFF_Remainder_IP 46048
#define SetHWScoreboard_MBAFF_Remainder_Loop_IP 46272
#define SET_SB_MBAFF_REM_INTRA_IP 46576
#define SET_SB_MBAFF_REM_IP 46768
#define Output_MBAFF_Remainder_Intra_IP 46848
#define SetHWScoreboard_MBAFF_Done_IP 46944
#define BSDRESET_IP 46960
#define DCRESETDUMMY_IP 46976
#define AllAVC_END_IP 46992
#define INTRA_16x16_VERTICAL_IP 14
#define INTRA_16x16_HORIZONTAL_IP 32
#define INTRA_16x16_DC_IP 52
#define INTRA_16x16_PLANE_IP 98
#define End_intra_Pred_16x16_Y_IP 166
#define End_add_Error_16x16_Y_IP 204
#define load_Intra_Ref_Y_IP 220
#define decode_Chroma_Intra_IP 238
#define INTRA_CHROMA_DC_IP 260
#define INTRA_CHROMA_HORIZONTAL_IP 320
#define INTRA_CHROMA_VERTICAL_IP 332
#define INTRA_Chroma_PLANE_IP 342
#define End_of_intra_Pred_Chroma_IP 392
#define save_16x16_Y_IP 436
#define INTRA_8x8_IP 464
#define INTRA_8x8_BLK2_IP 568
#define intra_Pred_8x8_Y_IP 640
#define INTRA_8X8_VERTICAL_IP 672
#define INTRA_8X8_HORIZONTAL_IP 682
#define INTRA_8X8_DC_IP 692
#define INTRA_8X8_DIAG_DOWN_LEFT_IP 724
#define INTRA_8X8_DIAG_DOWN_RIGHT_IP 744
#define INTRA_8X8_VERT_RIGHT_IP 772
#define INTRA_8X8_HOR_DOWN_IP 808
#define INTRA_8X8_VERT_LEFT_IP 842
#define INTRA_8X8_HOR_UP_IP 862
#define save_8x8_Y_IP 886
#define INTRA_4x4_IP 928
#define intra_Pred_4x4_Y_4_IP 1062
#define ADD_ERROR_SB0_IP 1074
#define ADD_ERROR_SB1_IP 1088
#define ADD_ERROR_SB2_IP 1108
#define ADD_ERROR_SB3_IP 1124
#define intra_Pred_4x4_Y_IP 1130
#define INTRA_4X4_VERTICAL_IP 1130
#define INTRA_4X4_HORIZONTAL_IP 1134
#define INTRA_4X4_DC_IP 1138
#define INTRA_4X4_DIAG_DOWN_LEFT_IP 1160
#define INTRA_4X4_DIAG_DOWN_RIGHT_IP 1174
#define INTRA_4X4_VERT_RIGHT_IP 1192
#define INTRA_4X4_HOR_DOWN_IP 1218
#define INTRA_4X4_VERT_LEFT_IP 1246
#define INTRA_4X4_HOR_UP_IP 1260
#define save_4x4_Y_IP 1276
#define INTRA_PCM_IP 1320
#define FRAME_MB_IP 1384
#define INIT_MBPARA_FRM_IP 1390
#define NOT_8x8_MODE_FRM_IP 1426
#define CONVERT_MVS_FRM_IP 1436
#define INIT_ADDRESS_REGS_FRM_IP 1446
#define LOOP_SUBMB_FRM_IP 1454
#define LOOP_DIR_FRM_IP 1460
#define LOADREF_MVXZERO_FRM_IP 1510
#define EXIT_LOADREF_Y_16x13_FRM_IP 1524
#define Interpolate_Y_8x8_Func_FRM_IP 1544
#define Interpolate_Y_8x8_Func2_FRM_IP 1574
#define Interpolate_Y_H_8x8_FRM_IP 1708
#define Interpolate_Y_V_8x8_FRM_IP 1790
#define VFILTER_8x8_FRM_IP 1812
#define Interpolate_Y_I_8x8_FRM_IP 1860
#define Average_8x8_FRM_IP 1880
#define Return_Interpolate_Y_8x8_FRM_IP 1888
#define Exit_Interpolate_Y_8x8_FRM_IP 1890
#define Interpolate_C_4x4_Func_FRM_IP 1890
#define PROCESS4x4_FRM_IP 1928
#define LOOP_SUBMBPT_FRM_IP 1930
#define Interpolate_Y_H_4x4_FRM_IP 2066
#define Interpolate_Y_V_4x4_FRM_IP 2108
#define VFILTER_4x4_FRM_IP 2142
#define Interpolate_Y_I_4x4_FRM_IP 2148
#define Average_4x4_FRM_IP 2160
#define Return_Interpolate_Y_4x4_FRM_IP 2162
#define Exit_Interpolate_Y_4x4_FRM_IP 2174
#define ROUND_SHIFT_C_FRM_IP 2222
#define LOOP_DIR_CONTINUE_FRM_IP 2230
#define Weighted_Prediction_FRM_IP 2236
#define DefaultWeightedPred_UniPred_FRM_IP 2244
#define DefaultWeightedPred_BiPred_FRM_IP 2256
#define WeightedPred_FRM_IP 2264
#define WeightedPred_Explicit_FRM_IP 2282
#define WeightedPred_LOOP_FRM_IP 2322
#define Return_WeightedPred_FRM_IP 2382
#define EXIT_LOOP_FRM_IP 2424
#define FIELD_MB_IP 2496
#define INIT_MBPARA_FLD_IP 2502
#define NOT_8x8_MODE_FLD_IP 2538
#define CONVERT_MVS_FLD_IP 2548
#define INIT_ADDRESS_REGS_FLD_IP 2558
#define LOOP_SUBMB_FLD_IP 2568
#define LOOP_DIR_FLD_IP 2574
#define LOADREF_MVXZERO_FLD_IP 2644
#define EXIT_LOADREF_Y_16x13_FLD_IP 2658
#define Interpolate_Y_8x8_Func_FLD_IP 2680
#define Interpolate_Y_8x8_Func2_FLD_IP 2710
#define Interpolate_Y_H_8x8_FLD_IP 2844
#define Interpolate_Y_V_8x8_FLD_IP 2926
#define VFILTER_8x8_FLD_IP 2948
#define Interpolate_Y_I_8x8_FLD_IP 2996
#define Average_8x8_FLD_IP 3016
#define Return_Interpolate_Y_8x8_FLD_IP 3024
#define Exit_Interpolate_Y_8x8_FLD_IP 3026
#define Interpolate_C_4x4_Func_FLD_IP 3026
#define PROCESS4x4_FLD_IP 3064
#define LOOP_SUBMBPT_FLD_IP 3066
#define Interpolate_Y_H_4x4_FLD_IP 3204
#define Interpolate_Y_V_4x4_FLD_IP 3246
#define VFILTER_4x4_FLD_IP 3280
#define Interpolate_Y_I_4x4_FLD_IP 3286
#define Average_4x4_FLD_IP 3298
#define Return_Interpolate_Y_4x4_FLD_IP 3300
#define Exit_Interpolate_Y_4x4_FLD_IP 3312
#define ROUND_SHIFT_C_FLD_IP 3360
#define LOOP_DIR_CONTINUE_FLD_IP 3368
#define Weighted_Prediction_FLD_IP 3374
#define DefaultWeightedPred_UniPred_FLD_IP 3382
#define DefaultWeightedPred_BiPred_FLD_IP 3394
#define WeightedPred_FLD_IP 3402
#define WeightedPred_Explicit_FLD_IP 3420
#define WeightedPred_LOOP_FLD_IP 3460
#define Return_WeightedPred_FLD_IP 3520
#define EXIT_LOOP_FLD_IP 3562
#define MBAFF_MB_IP 3640
#define INIT_MBPARA_MBF_IP 3646
#define NOT_8x8_MODE_MBF_IP 3682
#define CONVERT_MVS_MBF_IP 3692
#define INIT_ADDRESS_REGS_MBF_IP 3702
#define LOOP_SUBMB_MBF_IP 3716
#define LOOP_DIR_MBF_IP 3722
#define LOADREF_MVXZERO_MBF_IP 3796
#define EXIT_LOADREF_Y_16x13_MBF_IP 3810
#define Interpolate_Y_8x8_Func_MBF_IP 3832
#define Interpolate_Y_8x8_Func2_MBF_IP 3862
#define Interpolate_Y_H_8x8_MBF_IP 3996
#define Interpolate_Y_V_8x8_MBF_IP 4078
#define VFILTER_8x8_MBF_IP 4100
#define Interpolate_Y_I_8x8_MBF_IP 4148
#define Average_8x8_MBF_IP 4168
#define Return_Interpolate_Y_8x8_MBF_IP 4176
#define Exit_Interpolate_Y_8x8_MBF_IP 4178
#define Interpolate_C_4x4_Func_MBF_IP 4178
#define PROCESS4x4_MBF_IP 4216
#define LOOP_SUBMBPT_MBF_IP 4218
#define Interpolate_Y_H_4x4_MBF_IP 4356
#define Interpolate_Y_V_4x4_MBF_IP 4398
#define VFILTER_4x4_MBF_IP 4432
#define Interpolate_Y_I_4x4_MBF_IP 4438
#define Average_4x4_MBF_IP 4450
#define Return_Interpolate_Y_4x4_MBF_IP 4452
#define Exit_Interpolate_Y_4x4_MBF_IP 4464
#define ROUND_SHIFT_C_MBF_IP 4512
#define LOOP_DIR_CONTINUE_MBF_IP 4520
#define Weighted_Prediction_MBF_IP 4526
#define DefaultWeightedPred_UniPred_MBF_IP 4534
#define DefaultWeightedPred_BiPred_MBF_IP 4546
#define WeightedPred_MBF_IP 4554
#define WeightedPred_Explicit_MBF_IP 4572
#define WeightedPred_LOOP_MBF_IP 4612
#define Return_WeightedPred_MBF_IP 4672
#define EXIT_LOOP_MBF_IP 4714
#define SETHWSCOREBOARD_IP 4792
#define SetHWScoreboard_Loop_IP 4806
#define Parse_8_Loop_0_IP 4852
#define Parse_8_Loop_2_IP 4876
#define Parse_8_Loop_4_IP 4900
#define Parse_8_Loop_6_IP 4924
#define Parse_8_Loop_8_IP 4948
#define Parse_8_Loop_10_IP 4972
#define Parse_8_Loop_12_IP 4996
#define Parse_8_Loop_14_IP 5020
#define SetHWScoreboard_Remainder_IP 5062
#define SetHWScoreboard_Remainder_Loop_IP 5090
#define Output_Remainder_Intra_IP 5116
#define SetHWScoreboard_Done_IP 5128
#define SETHWSCOREBOARD_MBAFF_IP 5136
#define SetHWScoreboard_MBAFF_Loop_IP 5148
#define SET_SB_MBAFF_INTRA_0_IP 5208
#define SET_SB_MBAFF_0_IP 5230
#define NEXT_MB_MBAFF_0_IP 5238
#define SET_SB_MBAFF_INTRA_2_IP 5276
#define SET_SB_MBAFF_2_IP 5298
#define NEXT_MB_MBAFF_2_IP 5306
#define SET_SB_MBAFF_INTRA_4_IP 5344
#define SET_SB_MBAFF_4_IP 5366
#define NEXT_MB_MBAFF_4_IP 5374
#define SET_SB_MBAFF_INTRA_6_IP 5412
#define SET_SB_MBAFF_6_IP 5434
#define NEXT_MB_MBAFF_6_IP 5442
#define SET_SB_MBAFF_INTRA_8_IP 5480
#define SET_SB_MBAFF_8_IP 5502
#define NEXT_MB_MBAFF_8_IP 5510
#define SET_SB_MBAFF_INTRA_10_IP 5548
#define SET_SB_MBAFF_10_IP 5570
#define NEXT_MB_MBAFF_10_IP 5578
#define SET_SB_MBAFF_INTRA_12_IP 5616
#define SET_SB_MBAFF_12_IP 5638
#define NEXT_MB_MBAFF_12_IP 5646
#define SET_SB_MBAFF_INTRA_14_IP 5684
#define SET_SB_MBAFF_14_IP 5706
#define NEXT_MB_MBAFF_14_IP 5714
#define SetHWScoreboard_MBAFF_Remainder_IP 5756
#define SetHWScoreboard_MBAFF_Remainder_Loop_IP 5784
#define SET_SB_MBAFF_REM_INTRA_IP 5822
#define SET_SB_MBAFF_REM_IP 5846
#define Output_MBAFF_Remainder_Intra_IP 5856
#define SetHWScoreboard_MBAFF_Done_IP 5868
#define BSDRESET_IP 5870
#define DCRESETDUMMY_IP 5872
#define AVC_ILDB_ROOT_Y_ILDB_FRAME_IP 5880
#define SLEEP_ENTRY_Y_ILDB_FRAME_IP 5976
#define POST_SLEEP_Y_ILDB_FRAME_IP 5980
#define NEXT_MB_Y_ILDB_FRAME_IP 6010
#define ALL_SPAWNED_Y_ILDB_FRAME_IP 6034
#define ALL_DONE_Y_ILDB_FRAME_IP 6044
#define WAIT_FOR_UV_ILDB_FRAME_IP 6044
#define AVC_ILDB_CHILD_Y_ILDB_FRAME_IP 6056
#define WRITE_URB_Y_ILDB_FRAME_IP 6436
#define POST_ILDB_Y_ILDB_FRAME_IP 6444
#define READ_FOR_URB_Y_ILDB_FRAME_IP 6458
#define FILTER_Y_IP 6494
#define Y_ELSE3_IP 6560
#define Y_ENDIF3_IP 6574
#define Y_ELSE4_IP 6604
#define Y_ENDIF4_IP 6618
#define Y_ELSE2_IP 6618
#define Y_ENDIF6_IP 6684
#define Y_ENDIF7_IP 6706
#define Y_ENDIF2_IP 6710
#define Y_ENDIF1_IP 6710
#define AVC_ILDB_ROOT_UV_ILDB_FRAME_IP 6720
#define SLEEP_ENTRY_UV_ILDB_FRAME_IP 6798
#define POST_SLEEP_UV_ILDB_FRAME_IP 6802
#define NEXT_MB_UV_ILDB_FRAME_IP 6834
#define ALL_SPAWNED_UV_ILDB_FRAME_IP 6858
#define ALL_DONE_UV_ILDB_FRAME_IP 6882
#define AVC_ILDB_CHILD_UV_ILDB_FRAME_IP 6888
#define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FRAME_IP 7008
#define BYPASS_EXT_TOP_EDGE_UV_ILDB_FRAME_IP 7126
#define WRITE_URB_UV_ILDB_FRAME_IP 7194
#define POST_ILDB_UV_ILDB_FRAME_IP 7202
#define READ_FOR_URB_UV_ILDB_FRAME_IP 7216
#define FILTER_UV_IP 7246
#define UV_ELSE2_IP 7282
#define UV_ENDIF2_IP 7314
#define UV_ENDIF1_IP 7314
#define AVC_ILDB_ROOT_Y_ILDB_FIELD_IP 7320
#define SLEEP_ENTRY_Y_ILDB_FIELD_IP 7416
#define POST_SLEEP_Y_ILDB_FIELD_IP 7420
#define NEXT_MB_Y_ILDB_FIELD_IP 7450
#define ALL_SPAWNED_Y_ILDB_FIELD_IP 7474
#define ALL_DONE_Y_ILDB_FIELD_IP 7484
#define WAIT_FOR_UV_ILDB_FIELD_IP 7484
#define AVC_ILDB_CHILD_Y_ILDB_FIELD_IP 7496
#define WRITE_URB_Y_ILDB_FIELD_IP 7896
#define POST_ILDB_Y_ILDB_FIELD_IP 7904
#define READ_FOR_URB_Y_ILDB_FIELD_IP 7918
#define ELSE_Y_4x16T_ILDB_FIELD_IP 7934
#define ENDIF_Y_4x16T_ILDB_FIELD_IP 7942
#define AVC_ILDB_ROOT_UV_ILDB_FIELD_IP 7976
#define SLEEP_ENTRY_UV_ILDB_FIELD_IP 8054
#define POST_SLEEP_UV_ILDB_FIELD_IP 8058
#define NEXT_MB_UV_ILDB_FIELD_IP 8090
#define ALL_SPAWNED_UV_ILDB_FIELD_IP 8114
#define ALL_DONE_UV_ILDB_FIELD_IP 8138
#define AVC_ILDB_CHILD_UV_ILDB_FIELD_IP 8144
#define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FIELD_IP 8272
#define BYPASS_EXT_TOP_EDGE_UV_ILDB_FIELD_IP 8394
#define WRITE_URB_UV_ILDB_FIELD_IP 8470
#define POST_ILDB_UV_ILDB_FIELD_IP 8478
#define READ_FOR_URB_UV_ILDB_FIELD_IP 8492
#define ELSE_Y_2x8T_ILDB_FIELD_IP 8508
#define ENDIF_Y_2x8T_ILDB_FIELD_IP 8516
#define AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP 8544
#define SLEEP_ENTRY_Y_ILDB_MBAFF_IP 8642
#define POST_SLEEP_Y_ILDB_MBAFF_IP 8646
#define NEXT_MB_Y_ILDB_MBAFF_IP 8676
#define ALL_SPAWNED_Y_ILDB_MBAFF_IP 8700
#define ALL_DONE_Y_ILDB_MBAFF_IP 8710
#define WAIT_FOR_UV_ILDB_MBAFF_IP 8710
#define AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP 8720
#define RE_ENTRY_IP 8742
#define ELSE_Y_16x16T_ILDB_MBAFF_IP 8782
#define ENDIF_Y_16x16T_ILDB_MBAFF_IP 8792
#define ELSE_Y_4x16T_IP 8808
#define ENDIF_Y_4x16T_IP 8818
#define BYPASS_V1_Y_IP 8966
#define BYPASS_V2_Y_IP 8980
#define BYPASS_V3_Y_IP 8994
#define ELSE_Y_16x4T_IP 9024
#define ENDIF_Y_16x4T_IP 9034
#define NOT_DUAL_FIELD_IP 9060
#define ELSE_Y_16x4_IP 9060
#define ENDIF_Y_16x4_IP 9072
#define DUAL_FIELD_Y_IP 9168
#define H0_Y_DONE_IP 9236
#define ELSE_Y_16x16_IP 9310
#define ENDIF_Y_16x16_IP 9320
#define ELSE_Y_16x4_SAVE_IP 9342
#define ENDIF_Y_16x4_SAVE_IP 9354
#define SKIP_ILDB_IP 9356
#define POST_ILDB_IP 9364
#define FILTER_Y_MBAFF_IP 9378
#define MBAFF_Y_ELSE3_IP 9444
#define MBAFF_Y_ENDIF3_IP 9458
#define MBAFF_Y_ELSE4_IP 9488
#define MBAFF_Y_ENDIF4_IP 9502
#define MBAFF_Y_ELSE2_IP 9502
#define MBAFF_Y_ENDIF6_IP 9566
#define MBAFF_Y_ENDIF7_IP 9588
#define MBAFF_Y_ENDIF2_IP 9592
#define MBAFF_Y_ENDIF1_IP 9592
#define AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP 9600
#define SLEEP_ENTRY_UV_ILDB_MBAFF_IP 9678
#define POST_SLEEP_UV_ILDB_MBAFF_IP 9682
#define NEXT_MB_UV_ILDB_MBAFF_IP 9714
#define ALL_SPAWNED_UV_ILDB_MBAFF_IP 9738
#define ALL_DONE_UV_ILDB_MBAFF_IP 9762
#define AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP 9768
#define RE_ENTRY_UV_ILDB_MBAFF_IP 9794
#define ELSE_UV_8X8T_ILDB_MBAFF_IP 9836
#define ENDIF_UV_8X8T_ILDB_MBAFF_IP 9846
#define ELSE_Y_2x8T_ILDB_MBAFF_IP 9864
#define ENDIF_Y_2x8T_ILDB_MBAFF_IP 9874
#define V0_U_NEXT1_IP 9934
#define V0_U_NEXT2_IP 9954
#define V0_U_NEXT3_IP 9964
#define BYPASS_V0_UV_IP 10018
#define ELSE_UV_8X2T_IP 10082
#define ENDIF_UV_8X2T_IP 10092
#define NOT_DUAL_FIELD_UV_IP 10120
#define ELSE_UV_8X2_IP 10120
#define ENDIF_UV_8X2_IP 10132
#define DUAL_FIELD_UV_IP 10208
#define H0_UV_DONE_IP 10300
#define ELSE_UV_8X8_IP 10360
#define ENDIF_UV_8X8_IP 10370
#define ELSE_UV_8X2_SAVE_IP 10394
#define ENDIF_UV_8X2_SAVE_IP 10406
#define SKIP_ILDB_UV_ILDB_MBAFF_IP 10408
#define POST_ILDB_UV_ILDB_MBAFF_IP 10416
#define FILTER_UV_MBAFF_IP 10430
#define MBAFF_UV_ELSE2_IP 10466
#define MBAFF_UV_ENDIF2_IP 10496
#define MBAFF_UV_ENDIF1_IP 10496
#define AllAVC_END_IP 10500
i965_drv_video/shaders/h264/mc/export.inc.gen5
View file @ 8af77b87
#define INTRA_16x16_IP_GEN5 0
#define INTRA_16x16_VERTICAL_IP_GEN5 112
#define INTRA_16x16_HORIZONTAL_IP_GEN5 256
#define INTRA_16x16_DC_IP_GEN5 416
#define INTRA_16x16_PLANE_IP_GEN5 784
#define End_intra_Pred_16x16_Y_IP_GEN5 1328
#define End_add_Error_16x16_Y_IP_GEN5 1632
#define load_Intra_Ref_Y_IP_GEN5 1760
#define decode_Chroma_Intra_IP_GEN5 1904
#define INTRA_CHROMA_DC_IP_GEN5 2080
#define INTRA_CHROMA_HORIZONTAL_IP_GEN5 2560
#define INTRA_CHROMA_VERTICAL_IP_GEN5 2656
#define INTRA_Chroma_PLANE_IP_GEN5 2736
#define End_of_intra_Pred_Chroma_IP_GEN5 3136
#define save_16x16_Y_IP_GEN5 3488
#define INTRA_8x8_IP_GEN5 3712
#define INTRA_8x8_BLK2_IP_GEN5 4544
#define intra_Pred_8x8_Y_IP_GEN5 5120
#define INTRA_8X8_VERTICAL_IP_GEN5 5376
#define INTRA_8X8_HORIZONTAL_IP_GEN5 5456
#define INTRA_8X8_DC_IP_GEN5 5536
#define INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 5792
#define INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 5952
#define INTRA_8X8_VERT_RIGHT_IP_GEN5 6176
#define INTRA_8X8_HOR_DOWN_IP_GEN5 6464
#define INTRA_8X8_VERT_LEFT_IP_GEN5 6736
#define INTRA_8X8_HOR_UP_IP_GEN5 6896
#define save_8x8_Y_IP_GEN5 7088
#define INTRA_4x4_IP_GEN5 7424
#define intra_Pred_4x4_Y_4_IP_GEN5 8496
#define ADD_ERROR_SB0_IP_GEN5 8592
#define ADD_ERROR_SB1_IP_GEN5 8704
#define ADD_ERROR_SB2_IP_GEN5 8864
#define ADD_ERROR_SB3_IP_GEN5 8992
#define intra_Pred_4x4_Y_IP_GEN5 9040
#define INTRA_4X4_VERTICAL_IP_GEN5 9040
#define INTRA_4X4_HORIZONTAL_IP_GEN5 9072
#define INTRA_4X4_DC_IP_GEN5 9104
#define INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 9280
#define INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 9392
#define INTRA_4X4_VERT_RIGHT_IP_GEN5 9536
#define INTRA_4X4_HOR_DOWN_IP_GEN5 9744
#define INTRA_4X4_VERT_LEFT_IP_GEN5 9968
#define INTRA_4X4_HOR_UP_IP_GEN5 10080
#define save_4x4_Y_IP_GEN5 10208
#define INTRA_PCM_IP_GEN5 10560
#define FRAME_MB_IP_GEN5 11072
#define INIT_MBPARA_FRM_IP_GEN5 11120
#define NOT_8x8_MODE_FRM_IP_GEN5 11408
#define CONVERT_MVS_FRM_IP_GEN5 11488
#define INIT_ADDRESS_REGS_FRM_IP_GEN5 11568
#define LOOP_SUBMB_FRM_IP_GEN5 11632
#define LOOP_DIR_FRM_IP_GEN5 11680
#define LOADREF_MVXZERO_FRM_IP_GEN5 12080
#define EXIT_LOADREF_Y_16x13_FRM_IP_GEN5 12192
#define Interpolate_Y_8x8_Func_FRM_IP_GEN5 12352
#define Interpolate_Y_8x8_Func2_FRM_IP_GEN5 12592
#define Interpolate_Y_H_8x8_FRM_IP_GEN5 13664
#define Interpolate_Y_V_8x8_FRM_IP_GEN5 14320
#define VFILTER_8x8_FRM_IP_GEN5 14496
#define Interpolate_Y_I_8x8_FRM_IP_GEN5 14880
#define Average_8x8_FRM_IP_GEN5 15040
#define Return_Interpolate_Y_8x8_FRM_IP_GEN5 15104
#define Exit_Interpolate_Y_8x8_FRM_IP_GEN5 15120
#define Interpolate_C_4x4_Func_FRM_IP_GEN5 15120
#define PROCESS4x4_FRM_IP_GEN5 15424
#define LOOP_SUBMBPT_FRM_IP_GEN5 15440
#define Interpolate_Y_H_4x4_FRM_IP_GEN5 16528
#define Interpolate_Y_V_4x4_FRM_IP_GEN5 16864
#define VFILTER_4x4_FRM_IP_GEN5 17136
#define Interpolate_Y_I_4x4_FRM_IP_GEN5 17184
#define Average_4x4_FRM_IP_GEN5 17280
#define Return_Interpolate_Y_4x4_FRM_IP_GEN5 17296
#define Exit_Interpolate_Y_4x4_FRM_IP_GEN5 17392
#define ROUND_SHIFT_C_FRM_IP_GEN5 17776
#define LOOP_DIR_CONTINUE_FRM_IP_GEN5 17840
#define Weighted_Prediction_FRM_IP_GEN5 17888
#define DefaultWeightedPred_UniPred_FRM_IP_GEN5 17952
#define DefaultWeightedPred_BiPred_FRM_IP_GEN5 18048
#define WeightedPred_FRM_IP_GEN5 18112
#define WeightedPred_Explicit_FRM_IP_GEN5 18256
#define WeightedPred_LOOP_FRM_IP_GEN5 18576
#define Return_WeightedPred_FRM_IP_GEN5 19056
#define EXIT_LOOP_FRM_IP_GEN5 19392
#define FIELD_MB_IP_GEN5 19968
#define INIT_MBPARA_FLD_IP_GEN5 20016
#define NOT_8x8_MODE_FLD_IP_GEN5 20304
#define CONVERT_MVS_FLD_IP_GEN5 20384
#define INIT_ADDRESS_REGS_FLD_IP_GEN5 20464
#define LOOP_SUBMB_FLD_IP_GEN5 20544
#define LOOP_DIR_FLD_IP_GEN5 20592
#define LOADREF_MVXZERO_FLD_IP_GEN5 21152
#define EXIT_LOADREF_Y_16x13_FLD_IP_GEN5 21264
#define Interpolate_Y_8x8_Func_FLD_IP_GEN5 21440
#define Interpolate_Y_8x8_Func2_FLD_IP_GEN5 21680
#define Interpolate_Y_H_8x8_FLD_IP_GEN5 22752
#define Interpolate_Y_V_8x8_FLD_IP_GEN5 23408
#define VFILTER_8x8_FLD_IP_GEN5 23584
#define Interpolate_Y_I_8x8_FLD_IP_GEN5 23968
#define Average_8x8_FLD_IP_GEN5 24128
#define Return_Interpolate_Y_8x8_FLD_IP_GEN5 24192
#define Exit_Interpolate_Y_8x8_FLD_IP_GEN5 24208
#define Interpolate_C_4x4_Func_FLD_IP_GEN5 24208
#define PROCESS4x4_FLD_IP_GEN5 24512
#define LOOP_SUBMBPT_FLD_IP_GEN5 24528
#define Interpolate_Y_H_4x4_FLD_IP_GEN5 25632
#define Interpolate_Y_V_4x4_FLD_IP_GEN5 25968
#define VFILTER_4x4_FLD_IP_GEN5 26240
#define Interpolate_Y_I_4x4_FLD_IP_GEN5 26288
#define Average_4x4_FLD_IP_GEN5 26384
#define Return_Interpolate_Y_4x4_FLD_IP_GEN5 26400
#define Exit_Interpolate_Y_4x4_FLD_IP_GEN5 26496
#define ROUND_SHIFT_C_FLD_IP_GEN5 26880
#define LOOP_DIR_CONTINUE_FLD_IP_GEN5 26944
#define Weighted_Prediction_FLD_IP_GEN5 26992
#define DefaultWeightedPred_UniPred_FLD_IP_GEN5 27056
#define DefaultWeightedPred_BiPred_FLD_IP_GEN5 27152
#define WeightedPred_FLD_IP_GEN5 27216
#define WeightedPred_Explicit_FLD_IP_GEN5 27360
#define WeightedPred_LOOP_FLD_IP_GEN5 27680
#define Return_WeightedPred_FLD_IP_GEN5 28160
#define EXIT_LOOP_FLD_IP_GEN5 28496
#define MBAFF_MB_IP_GEN5 29120
#define INIT_MBPARA_MBF_IP_GEN5 29168
#define NOT_8x8_MODE_MBF_IP_GEN5 29456
#define CONVERT_MVS_MBF_IP_GEN5 29536
#define INIT_ADDRESS_REGS_MBF_IP_GEN5 29616
#define LOOP_SUBMB_MBF_IP_GEN5 29728
#define LOOP_DIR_MBF_IP_GEN5 29776
#define LOADREF_MVXZERO_MBF_IP_GEN5 30368
#define EXIT_LOADREF_Y_16x13_MBF_IP_GEN5 30480
#define Interpolate_Y_8x8_Func_MBF_IP_GEN5 30656
#define Interpolate_Y_8x8_Func2_MBF_IP_GEN5 30896
#define Interpolate_Y_H_8x8_MBF_IP_GEN5 31968
#define Interpolate_Y_V_8x8_MBF_IP_GEN5 32624
#define VFILTER_8x8_MBF_IP_GEN5 32800
#define Interpolate_Y_I_8x8_MBF_IP_GEN5 33184
#define Average_8x8_MBF_IP_GEN5 33344
#define Return_Interpolate_Y_8x8_MBF_IP_GEN5 33408
#define Exit_Interpolate_Y_8x8_MBF_IP_GEN5 33424
#define Interpolate_C_4x4_Func_MBF_IP_GEN5 33424
#define PROCESS4x4_MBF_IP_GEN5 33728
#define LOOP_SUBMBPT_MBF_IP_GEN5 33744
#define Interpolate_Y_H_4x4_MBF_IP_GEN5 34848
#define Interpolate_Y_V_4x4_MBF_IP_GEN5 35184
#define VFILTER_4x4_MBF_IP_GEN5 35456
#define Interpolate_Y_I_4x4_MBF_IP_GEN5 35504
#define Average_4x4_MBF_IP_GEN5 35600
#define Return_Interpolate_Y_4x4_MBF_IP_GEN5 35616
#define Exit_Interpolate_Y_4x4_MBF_IP_GEN5 35712
#define ROUND_SHIFT_C_MBF_IP_GEN5 36096
#define LOOP_DIR_CONTINUE_MBF_IP_GEN5 36160
#define Weighted_Prediction_MBF_IP_GEN5 36208
#define DefaultWeightedPred_UniPred_MBF_IP_GEN5 36272
#define DefaultWeightedPred_BiPred_MBF_IP_GEN5 36368
#define WeightedPred_MBF_IP_GEN5 36432
#define WeightedPred_Explicit_MBF_IP_GEN5 36576
#define WeightedPred_LOOP_MBF_IP_GEN5 36896
#define Return_WeightedPred_MBF_IP_GEN5 37376
#define EXIT_LOOP_MBF_IP_GEN5 37712
#define SETHWSCOREBOARD_IP_GEN5 38336
#define SetHWScoreboard_Loop_IP_GEN5 38448
#define Parse_8_Loop_0_IP_GEN5 38816
#define Parse_8_Loop_2_IP_GEN5 39008
#define Parse_8_Loop_4_IP_GEN5 39200
#define Parse_8_Loop_6_IP_GEN5 39392
#define Parse_8_Loop_8_IP_GEN5 39584
#define Parse_8_Loop_10_IP_GEN5 39776
#define Parse_8_Loop_12_IP_GEN5 39968
#define Parse_8_Loop_14_IP_GEN5 40160
#define SetHWScoreboard_Remainder_IP_GEN5 40496
#define SetHWScoreboard_Remainder_Loop_IP_GEN5 40720
#define Output_Remainder_Intra_IP_GEN5 40928
#define SetHWScoreboard_Done_IP_GEN5 41024
#define SETHWSCOREBOARD_MBAFF_IP_GEN5 41088
#define SetHWScoreboard_MBAFF_Loop_IP_GEN5 41184
#define SET_SB_MBAFF_INTRA_0_IP_GEN5 41664
#define SET_SB_MBAFF_0_IP_GEN5 41840
#define NEXT_MB_MBAFF_0_IP_GEN5 41904
#define SET_SB_MBAFF_INTRA_2_IP_GEN5 42208
#define SET_SB_MBAFF_2_IP_GEN5 42384
#define NEXT_MB_MBAFF_2_IP_GEN5 42448
#define SET_SB_MBAFF_INTRA_4_IP_GEN5 42752
#define SET_SB_MBAFF_4_IP_GEN5 42928
#define NEXT_MB_MBAFF_4_IP_GEN5 42992
#define SET_SB_MBAFF_INTRA_6_IP_GEN5 43296
#define SET_SB_MBAFF_6_IP_GEN5 43472
#define NEXT_MB_MBAFF_6_IP_GEN5 43536
#define SET_SB_MBAFF_INTRA_8_IP_GEN5 43840
#define SET_SB_MBAFF_8_IP_GEN5 44016
#define NEXT_MB_MBAFF_8_IP_GEN5 44080
#define SET_SB_MBAFF_INTRA_10_IP_GEN5 44384
#define SET_SB_MBAFF_10_IP_GEN5 44560
#define NEXT_MB_MBAFF_10_IP_GEN5 44624
#define SET_SB_MBAFF_INTRA_12_IP_GEN5 44928
#define SET_SB_MBAFF_12_IP_GEN5 45104
#define NEXT_MB_MBAFF_12_IP_GEN5 45168
#define SET_SB_MBAFF_INTRA_14_IP_GEN5 45472
#define SET_SB_MBAFF_14_IP_GEN5 45648
#define NEXT_MB_MBAFF_14_IP_GEN5 45712
#define SetHWScoreboard_MBAFF_Remainder_IP_GEN5 46048
#define SetHWScoreboard_MBAFF_Remainder_Loop_IP_GEN5 46272
#define SET_SB_MBAFF_REM_INTRA_IP_GEN5 46576
#define SET_SB_MBAFF_REM_IP_GEN5 46768
#define Output_MBAFF_Remainder_Intra_IP_GEN5 46848
#define SetHWScoreboard_MBAFF_Done_IP_GEN5 46944
#define BSDRESET_IP_GEN5 46960
#define DCRESETDUMMY_IP_GEN5 46976
#define AllAVC_END_IP_GEN5 46992
#define INTRA_16x16_VERTICAL_IP_GEN5 14
#define INTRA_16x16_HORIZONTAL_IP_GEN5 32
#define INTRA_16x16_DC_IP_GEN5 52
#define INTRA_16x16_PLANE_IP_GEN5 98
#define End_intra_Pred_16x16_Y_IP_GEN5 166
#define End_add_Error_16x16_Y_IP_GEN5 204
#define load_Intra_Ref_Y_IP_GEN5 220
#define decode_Chroma_Intra_IP_GEN5 238
#define INTRA_CHROMA_DC_IP_GEN5 260
#define INTRA_CHROMA_HORIZONTAL_IP_GEN5 320
#define INTRA_CHROMA_VERTICAL_IP_GEN5 332
#define INTRA_Chroma_PLANE_IP_GEN5 342
#define End_of_intra_Pred_Chroma_IP_GEN5 392
#define save_16x16_Y_IP_GEN5 436
#define INTRA_8x8_IP_GEN5 464
#define INTRA_8x8_BLK2_IP_GEN5 568
#define intra_Pred_8x8_Y_IP_GEN5 640
#define INTRA_8X8_VERTICAL_IP_GEN5 672
#define INTRA_8X8_HORIZONTAL_IP_GEN5 682
#define INTRA_8X8_DC_IP_GEN5 692
#define INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 724
#define INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 744
#define INTRA_8X8_VERT_RIGHT_IP_GEN5 772
#define INTRA_8X8_HOR_DOWN_IP_GEN5 808
#define INTRA_8X8_VERT_LEFT_IP_GEN5 842
#define INTRA_8X8_HOR_UP_IP_GEN5 862
#define save_8x8_Y_IP_GEN5 886
#define INTRA_4x4_IP_GEN5 928
#define intra_Pred_4x4_Y_4_IP_GEN5 1062
#define ADD_ERROR_SB0_IP_GEN5 1074
#define ADD_ERROR_SB1_IP_GEN5 1088
#define ADD_ERROR_SB2_IP_GEN5 1108
#define ADD_ERROR_SB3_IP_GEN5 1124
#define intra_Pred_4x4_Y_IP_GEN5 1130
#define INTRA_4X4_VERTICAL_IP_GEN5 1130
#define INTRA_4X4_HORIZONTAL_IP_GEN5 1134
#define INTRA_4X4_DC_IP_GEN5 1138
#define INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 1160
#define INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 1174
#define INTRA_4X4_VERT_RIGHT_IP_GEN5 1192
#define INTRA_4X4_HOR_DOWN_IP_GEN5 1218
#define INTRA_4X4_VERT_LEFT_IP_GEN5 1246
#define INTRA_4X4_HOR_UP_IP_GEN5 1260
#define save_4x4_Y_IP_GEN5 1276
#define INTRA_PCM_IP_GEN5 1320
#define FRAME_MB_IP_GEN5 1384
#define INIT_MBPARA_FRM_IP_GEN5 1390
#define NOT_8x8_MODE_FRM_IP_GEN5 1426
#define CONVERT_MVS_FRM_IP_GEN5 1436
#define INIT_ADDRESS_REGS_FRM_IP_GEN5 1446
#define LOOP_SUBMB_FRM_IP_GEN5 1454
#define LOOP_DIR_FRM_IP_GEN5 1460
#define LOADREF_MVXZERO_FRM_IP_GEN5 1510
#define EXIT_LOADREF_Y_16x13_FRM_IP_GEN5 1524
#define Interpolate_Y_8x8_Func_FRM_IP_GEN5 1544
#define Interpolate_Y_8x8_Func2_FRM_IP_GEN5 1574
#define Interpolate_Y_H_8x8_FRM_IP_GEN5 1708
#define Interpolate_Y_V_8x8_FRM_IP_GEN5 1790
#define VFILTER_8x8_FRM_IP_GEN5 1812
#define Interpolate_Y_I_8x8_FRM_IP_GEN5 1860
#define Average_8x8_FRM_IP_GEN5 1880
#define Return_Interpolate_Y_8x8_FRM_IP_GEN5 1888
#define Exit_Interpolate_Y_8x8_FRM_IP_GEN5 1890
#define Interpolate_C_4x4_Func_FRM_IP_GEN5 1890
#define PROCESS4x4_FRM_IP_GEN5 1928
#define LOOP_SUBMBPT_FRM_IP_GEN5 1930
#define Interpolate_Y_H_4x4_FRM_IP_GEN5 2066
#define Interpolate_Y_V_4x4_FRM_IP_GEN5 2108
#define VFILTER_4x4_FRM_IP_GEN5 2142
#define Interpolate_Y_I_4x4_FRM_IP_GEN5 2148
#define Average_4x4_FRM_IP_GEN5 2160
#define Return_Interpolate_Y_4x4_FRM_IP_GEN5 2162
#define Exit_Interpolate_Y_4x4_FRM_IP_GEN5 2174
#define ROUND_SHIFT_C_FRM_IP_GEN5 2222
#define LOOP_DIR_CONTINUE_FRM_IP_GEN5 2230
#define Weighted_Prediction_FRM_IP_GEN5 2236
#define DefaultWeightedPred_UniPred_FRM_IP_GEN5 2244
#define DefaultWeightedPred_BiPred_FRM_IP_GEN5 2256
#define WeightedPred_FRM_IP_GEN5 2264
#define WeightedPred_Explicit_FRM_IP_GEN5 2282
#define WeightedPred_LOOP_FRM_IP_GEN5 2322
#define Return_WeightedPred_FRM_IP_GEN5 2382
#define EXIT_LOOP_FRM_IP_GEN5 2424
#define FIELD_MB_IP_GEN5 2496
#define INIT_MBPARA_FLD_IP_GEN5 2502
#define NOT_8x8_MODE_FLD_IP_GEN5 2538
#define CONVERT_MVS_FLD_IP_GEN5 2548
#define INIT_ADDRESS_REGS_FLD_IP_GEN5 2558
#define LOOP_SUBMB_FLD_IP_GEN5 2568
#define LOOP_DIR_FLD_IP_GEN5 2574
#define LOADREF_MVXZERO_FLD_IP_GEN5 2644
#define EXIT_LOADREF_Y_16x13_FLD_IP_GEN5 2658
#define Interpolate_Y_8x8_Func_FLD_IP_GEN5 2680
#define Interpolate_Y_8x8_Func2_FLD_IP_GEN5 2710
#define Interpolate_Y_H_8x8_FLD_IP_GEN5 2844
#define Interpolate_Y_V_8x8_FLD_IP_GEN5 2926
#define VFILTER_8x8_FLD_IP_GEN5 2948
#define Interpolate_Y_I_8x8_FLD_IP_GEN5 2996
#define Average_8x8_FLD_IP_GEN5 3016
#define Return_Interpolate_Y_8x8_FLD_IP_GEN5 3024
#define Exit_Interpolate_Y_8x8_FLD_IP_GEN5 3026
#define Interpolate_C_4x4_Func_FLD_IP_GEN5 3026
#define PROCESS4x4_FLD_IP_GEN5 3064
#define LOOP_SUBMBPT_FLD_IP_GEN5 3066
#define Interpolate_Y_H_4x4_FLD_IP_GEN5 3204
#define Interpolate_Y_V_4x4_FLD_IP_GEN5 3246
#define VFILTER_4x4_FLD_IP_GEN5 3280
#define Interpolate_Y_I_4x4_FLD_IP_GEN5 3286
#define Average_4x4_FLD_IP_GEN5 3298
#define Return_Interpolate_Y_4x4_FLD_IP_GEN5 3300
#define Exit_Interpolate_Y_4x4_FLD_IP_GEN5 3312
#define ROUND_SHIFT_C_FLD_IP_GEN5 3360
#define LOOP_DIR_CONTINUE_FLD_IP_GEN5 3368
#define Weighted_Prediction_FLD_IP_GEN5 3374
#define DefaultWeightedPred_UniPred_FLD_IP_GEN5 3382
#define DefaultWeightedPred_BiPred_FLD_IP_GEN5 3394
#define WeightedPred_FLD_IP_GEN5 3402
#define WeightedPred_Explicit_FLD_IP_GEN5 3420
#define WeightedPred_LOOP_FLD_IP_GEN5 3460
#define Return_WeightedPred_FLD_IP_GEN5 3520
#define EXIT_LOOP_FLD_IP_GEN5 3562
#define MBAFF_MB_IP_GEN5 3640
#define INIT_MBPARA_MBF_IP_GEN5 3646
#define NOT_8x8_MODE_MBF_IP_GEN5 3682
#define CONVERT_MVS_MBF_IP_GEN5 3692
#define INIT_ADDRESS_REGS_MBF_IP_GEN5 3702
#define LOOP_SUBMB_MBF_IP_GEN5 3716
#define LOOP_DIR_MBF_IP_GEN5 3722
#define LOADREF_MVXZERO_MBF_IP_GEN5 3796
#define EXIT_LOADREF_Y_16x13_MBF_IP_GEN5 3810
#define Interpolate_Y_8x8_Func_MBF_IP_GEN5 3832
#define Interpolate_Y_8x8_Func2_MBF_IP_GEN5 3862
#define Interpolate_Y_H_8x8_MBF_IP_GEN5 3996
#define Interpolate_Y_V_8x8_MBF_IP_GEN5 4078
#define VFILTER_8x8_MBF_IP_GEN5 4100
#define Interpolate_Y_I_8x8_MBF_IP_GEN5 4148
#define Average_8x8_MBF_IP_GEN5 4168
#define Return_Interpolate_Y_8x8_MBF_IP_GEN5 4176
#define Exit_Interpolate_Y_8x8_MBF_IP_GEN5 4178
#define Interpolate_C_4x4_Func_MBF_IP_GEN5 4178
#define PROCESS4x4_MBF_IP_GEN5 4216
#define LOOP_SUBMBPT_MBF_IP_GEN5 4218
#define Interpolate_Y_H_4x4_MBF_IP_GEN5 4356
#define Interpolate_Y_V_4x4_MBF_IP_GEN5 4398
#define VFILTER_4x4_MBF_IP_GEN5 4432
#define Interpolate_Y_I_4x4_MBF_IP_GEN5 4438
#define Average_4x4_MBF_IP_GEN5 4450
#define Return_Interpolate_Y_4x4_MBF_IP_GEN5 4452
#define Exit_Interpolate_Y_4x4_MBF_IP_GEN5 4464
#define ROUND_SHIFT_C_MBF_IP_GEN5 4512
#define LOOP_DIR_CONTINUE_MBF_IP_GEN5 4520
#define Weighted_Prediction_MBF_IP_GEN5 4526
#define DefaultWeightedPred_UniPred_MBF_IP_GEN5 4534
#define DefaultWeightedPred_BiPred_MBF_IP_GEN5 4546
#define WeightedPred_MBF_IP_GEN5 4554
#define WeightedPred_Explicit_MBF_IP_GEN5 4572
#define WeightedPred_LOOP_MBF_IP_GEN5 4612
#define Return_WeightedPred_MBF_IP_GEN5 4672
#define EXIT_LOOP_MBF_IP_GEN5 4714
#define SETHWSCOREBOARD_IP_GEN5 4792
#define SetHWScoreboard_Loop_IP_GEN5 4806
#define Parse_8_Loop_0_IP_GEN5 4852
#define Parse_8_Loop_2_IP_GEN5 4876
#define Parse_8_Loop_4_IP_GEN5 4900
#define Parse_8_Loop_6_IP_GEN5 4924
#define Parse_8_Loop_8_IP_GEN5 4948
#define Parse_8_Loop_10_IP_GEN5 4972
#define Parse_8_Loop_12_IP_GEN5 4996
#define Parse_8_Loop_14_IP_GEN5 5020
#define SetHWScoreboard_Remainder_IP_GEN5 5062
#define SetHWScoreboard_Remainder_Loop_IP_GEN5 5090
#define Output_Remainder_Intra_IP_GEN5 5116
#define SetHWScoreboard_Done_IP_GEN5 5128
#define SETHWSCOREBOARD_MBAFF_IP_GEN5 5136
#define SetHWScoreboard_MBAFF_Loop_IP_GEN5 5148
#define SET_SB_MBAFF_INTRA_0_IP_GEN5 5208
#define SET_SB_MBAFF_0_IP_GEN5 5230
#define NEXT_MB_MBAFF_0_IP_GEN5 5238
#define SET_SB_MBAFF_INTRA_2_IP_GEN5 5276
#define SET_SB_MBAFF_2_IP_GEN5 5298
#define NEXT_MB_MBAFF_2_IP_GEN5 5306
#define SET_SB_MBAFF_INTRA_4_IP_GEN5 5344
#define SET_SB_MBAFF_4_IP_GEN5 5366
#define NEXT_MB_MBAFF_4_IP_GEN5 5374
#define SET_SB_MBAFF_INTRA_6_IP_GEN5 5412
#define SET_SB_MBAFF_6_IP_GEN5 5434
#define NEXT_MB_MBAFF_6_IP_GEN5 5442
#define SET_SB_MBAFF_INTRA_8_IP_GEN5 5480
#define SET_SB_MBAFF_8_IP_GEN5 5502
#define NEXT_MB_MBAFF_8_IP_GEN5 5510
#define SET_SB_MBAFF_INTRA_10_IP_GEN5 5548
#define SET_SB_MBAFF_10_IP_GEN5 5570
#define NEXT_MB_MBAFF_10_IP_GEN5 5578
#define SET_SB_MBAFF_INTRA_12_IP_GEN5 5616
#define SET_SB_MBAFF_12_IP_GEN5 5638
#define NEXT_MB_MBAFF_12_IP_GEN5 5646
#define SET_SB_MBAFF_INTRA_14_IP_GEN5 5684
#define SET_SB_MBAFF_14_IP_GEN5 5706
#define NEXT_MB_MBAFF_14_IP_GEN5 5714
#define SetHWScoreboard_MBAFF_Remainder_IP_GEN5 5756
#define SetHWScoreboard_MBAFF_Remainder_Loop_IP_GEN5 5784
#define SET_SB_MBAFF_REM_INTRA_IP_GEN5 5822
#define SET_SB_MBAFF_REM_IP_GEN5 5846
#define Output_MBAFF_Remainder_Intra_IP_GEN5 5856
#define SetHWScoreboard_MBAFF_Done_IP_GEN5 5868
#define BSDRESET_IP_GEN5 5870
#define DCRESETDUMMY_IP_GEN5 5872
#define AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 5880
#define SLEEP_ENTRY_Y_ILDB_FRAME_IP_GEN5 5976
#define POST_SLEEP_Y_ILDB_FRAME_IP_GEN5 5980
#define NEXT_MB_Y_ILDB_FRAME_IP_GEN5 6010
#define ALL_SPAWNED_Y_ILDB_FRAME_IP_GEN5 6034
#define ALL_DONE_Y_ILDB_FRAME_IP_GEN5 6044
#define WAIT_FOR_UV_ILDB_FRAME_IP_GEN5 6044
#define AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 6056
#define WRITE_URB_Y_ILDB_FRAME_IP_GEN5 6436
#define POST_ILDB_Y_ILDB_FRAME_IP_GEN5 6444
#define READ_FOR_URB_Y_ILDB_FRAME_IP_GEN5 6458
#define FILTER_Y_IP_GEN5 6494
#define Y_ELSE3_IP_GEN5 6560
#define Y_ENDIF3_IP_GEN5 6574
#define Y_ELSE4_IP_GEN5 6604
#define Y_ENDIF4_IP_GEN5 6618
#define Y_ELSE2_IP_GEN5 6618
#define Y_ENDIF6_IP_GEN5 6684
#define Y_ENDIF7_IP_GEN5 6706
#define Y_ENDIF2_IP_GEN5 6710
#define Y_ENDIF1_IP_GEN5 6710
#define AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 6720
#define SLEEP_ENTRY_UV_ILDB_FRAME_IP_GEN5 6798
#define POST_SLEEP_UV_ILDB_FRAME_IP_GEN5 6802
#define NEXT_MB_UV_ILDB_FRAME_IP_GEN5 6834
#define ALL_SPAWNED_UV_ILDB_FRAME_IP_GEN5 6858
#define ALL_DONE_UV_ILDB_FRAME_IP_GEN5 6882
#define AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 6888
#define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FRAME_IP_GEN5 7008
#define BYPASS_EXT_TOP_EDGE_UV_ILDB_FRAME_IP_GEN5 7126
#define WRITE_URB_UV_ILDB_FRAME_IP_GEN5 7194
#define POST_ILDB_UV_ILDB_FRAME_IP_GEN5 7202
#define READ_FOR_URB_UV_ILDB_FRAME_IP_GEN5 7216
#define FILTER_UV_IP_GEN5 7246
#define UV_ELSE2_IP_GEN5 7282
#define UV_ENDIF2_IP_GEN5 7314
#define UV_ENDIF1_IP_GEN5 7314
#define AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 7320
#define SLEEP_ENTRY_Y_ILDB_FIELD_IP_GEN5 7416
#define POST_SLEEP_Y_ILDB_FIELD_IP_GEN5 7420
#define NEXT_MB_Y_ILDB_FIELD_IP_GEN5 7450
#define ALL_SPAWNED_Y_ILDB_FIELD_IP_GEN5 7474
#define ALL_DONE_Y_ILDB_FIELD_IP_GEN5 7484
#define WAIT_FOR_UV_ILDB_FIELD_IP_GEN5 7484
#define AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 7496
#define WRITE_URB_Y_ILDB_FIELD_IP_GEN5 7896
#define POST_ILDB_Y_ILDB_FIELD_IP_GEN5 7904
#define READ_FOR_URB_Y_ILDB_FIELD_IP_GEN5 7918
#define ELSE_Y_4x16T_ILDB_FIELD_IP_GEN5 7934
#define ENDIF_Y_4x16T_ILDB_FIELD_IP_GEN5 7942
#define AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 7976
#define SLEEP_ENTRY_UV_ILDB_FIELD_IP_GEN5 8054
#define POST_SLEEP_UV_ILDB_FIELD_IP_GEN5 8058
#define NEXT_MB_UV_ILDB_FIELD_IP_GEN5 8090
#define ALL_SPAWNED_UV_ILDB_FIELD_IP_GEN5 8114
#define ALL_DONE_UV_ILDB_FIELD_IP_GEN5 8138
#define AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 8144
#define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FIELD_IP_GEN5 8272
#define BYPASS_EXT_TOP_EDGE_UV_ILDB_FIELD_IP_GEN5 8394
#define WRITE_URB_UV_ILDB_FIELD_IP_GEN5 8470
#define POST_ILDB_UV_ILDB_FIELD_IP_GEN5 8478
#define READ_FOR_URB_UV_ILDB_FIELD_IP_GEN5 8492
#define ELSE_Y_2x8T_ILDB_FIELD_IP_GEN5 8508
#define ENDIF_Y_2x8T_ILDB_FIELD_IP_GEN5 8516
#define AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 8544
#define SLEEP_ENTRY_Y_ILDB_MBAFF_IP_GEN5 8642
#define POST_SLEEP_Y_ILDB_MBAFF_IP_GEN5 8646
#define NEXT_MB_Y_ILDB_MBAFF_IP_GEN5 8676
#define ALL_SPAWNED_Y_ILDB_MBAFF_IP_GEN5 8700
#define ALL_DONE_Y_ILDB_MBAFF_IP_GEN5 8710
#define WAIT_FOR_UV_ILDB_MBAFF_IP_GEN5 8710
#define AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 8720
#define RE_ENTRY_IP_GEN5 8742
#define ELSE_Y_16x16T_ILDB_MBAFF_IP_GEN5 8782
#define ENDIF_Y_16x16T_ILDB_MBAFF_IP_GEN5 8792
#define ELSE_Y_4x16T_IP_GEN5 8808
#define ENDIF_Y_4x16T_IP_GEN5 8818
#define BYPASS_V1_Y_IP_GEN5 8966
#define BYPASS_V2_Y_IP_GEN5 8980
#define BYPASS_V3_Y_IP_GEN5 8994
#define ELSE_Y_16x4T_IP_GEN5 9024
#define ENDIF_Y_16x4T_IP_GEN5 9034
#define NOT_DUAL_FIELD_IP_GEN5 9060
#define ELSE_Y_16x4_IP_GEN5 9060
#define ENDIF_Y_16x4_IP_GEN5 9072
#define DUAL_FIELD_Y_IP_GEN5 9168
#define H0_Y_DONE_IP_GEN5 9236
#define ELSE_Y_16x16_IP_GEN5 9310
#define ENDIF_Y_16x16_IP_GEN5 9320
#define ELSE_Y_16x4_SAVE_IP_GEN5 9342
#define ENDIF_Y_16x4_SAVE_IP_GEN5 9354
#define SKIP_ILDB_IP_GEN5 9356
#define POST_ILDB_IP_GEN5 9364
#define FILTER_Y_MBAFF_IP_GEN5 9378
#define MBAFF_Y_ELSE3_IP_GEN5 9444
#define MBAFF_Y_ENDIF3_IP_GEN5 9458
#define MBAFF_Y_ELSE4_IP_GEN5 9488
#define MBAFF_Y_ENDIF4_IP_GEN5 9502
#define MBAFF_Y_ELSE2_IP_GEN5 9502
#define MBAFF_Y_ENDIF6_IP_GEN5 9566
#define MBAFF_Y_ENDIF7_IP_GEN5 9588
#define MBAFF_Y_ENDIF2_IP_GEN5 9592
#define MBAFF_Y_ENDIF1_IP_GEN5 9592
#define AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 9600
#define SLEEP_ENTRY_UV_ILDB_MBAFF_IP_GEN5 9678
#define POST_SLEEP_UV_ILDB_MBAFF_IP_GEN5 9682
#define NEXT_MB_UV_ILDB_MBAFF_IP_GEN5 9714
#define ALL_SPAWNED_UV_ILDB_MBAFF_IP_GEN5 9738
#define ALL_DONE_UV_ILDB_MBAFF_IP_GEN5 9762
#define AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 9768
#define RE_ENTRY_UV_ILDB_MBAFF_IP_GEN5 9794
#define ELSE_UV_8X8T_ILDB_MBAFF_IP_GEN5 9836
#define ENDIF_UV_8X8T_ILDB_MBAFF_IP_GEN5 9846
#define ELSE_Y_2x8T_ILDB_MBAFF_IP_GEN5 9864
#define ENDIF_Y_2x8T_ILDB_MBAFF_IP_GEN5 9874
#define V0_U_NEXT1_IP_GEN5 9934
#define V0_U_NEXT2_IP_GEN5 9954
#define V0_U_NEXT3_IP_GEN5 9964
#define BYPASS_V0_UV_IP_GEN5 10018
#define ELSE_UV_8X2T_IP_GEN5 10082
#define ENDIF_UV_8X2T_IP_GEN5 10092
#define NOT_DUAL_FIELD_UV_IP_GEN5 10120
#define ELSE_UV_8X2_IP_GEN5 10120
#define ENDIF_UV_8X2_IP_GEN5 10132
#define DUAL_FIELD_UV_IP_GEN5 10208
#define H0_UV_DONE_IP_GEN5 10300
#define ELSE_UV_8X8_IP_GEN5 10360
#define ENDIF_UV_8X8_IP_GEN5 10370
#define ELSE_UV_8X2_SAVE_IP_GEN5 10394
#define ENDIF_UV_8X2_SAVE_IP_GEN5 10406
#define SKIP_ILDB_UV_ILDB_MBAFF_IP_GEN5 10408
#define POST_ILDB_UV_ILDB_MBAFF_IP_GEN5 10416
#define FILTER_UV_MBAFF_IP_GEN5 10430
#define MBAFF_UV_ELSE2_IP_GEN5 10466
#define MBAFF_UV_ENDIF2_IP_GEN5 10496
#define MBAFF_UV_ENDIF1_IP_GEN5 10496
#define AllAVC_END_IP_GEN5 10500
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