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Commit 6310eeee authored by Xiang, Haihao's avatar Xiang, Haihao
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i965_drv_video: Eanble VAAPI on IGDNG

parent c5133efd
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Showing with 375 additions and 51 deletions
i965_drv_video/i965_defines.h
View file @ 6310eeee
......@@ -321,5 +321,6 @@
#define I965_TILEWALK_XMAJOR 0
#define I965_TILEWALK_YMAJOR 1
#define URB_SIZE(intel) (IS_G4X(intel->device_id) ? 384 : 256)
#define URB_SIZE(intel) (IS_IGDNG(intel->device_id) ? 1024 : \
IS_G4X(intel->device_id) ? 384 : 256)
#endif /* _I965_DEFINES_H_ */
i965_drv_video/i965_drv_video.c
View file @ 6310eeee
......@@ -1105,7 +1105,8 @@ i965_Init(VADriverContextP ctx)
if (intel_driver_init(ctx) == False)
return VA_STATUS_ERROR_UNKNOWN;
if (!IS_G4X(i965->intel.device_id))
if (!IS_G4X(i965->intel.device_id) &&
!IS_IGDNG(i965->intel.device_id))
return VA_STATUS_ERROR_UNKNOWN;
if (i965_media_init(ctx) == False)
......
i965_drv_video/i965_media.c
View file @ 6310eeee
......@@ -71,6 +71,20 @@ i965_media_urb_layout(VADriverContextP ctx)
static void
i965_media_state_base_address(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
if (IS_IGDNG(i965->intel.device_id)) {
BEGIN_BATCH(ctx, 8);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
} else {
BEGIN_BATCH(ctx, 6);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
......@@ -79,6 +93,7 @@ i965_media_state_base_address(VADriverContextP ctx)
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
}
}
static void
......
i965_drv_video/i965_media_mpeg2.c
View file @ 6310eeee
......@@ -158,7 +158,7 @@ static uint32_t field_bidirect_16x8_kernel[][4] = {
#include "shaders/mpeg2/vld/field_bidirect_16x8.g4b"
};
static struct media_kernel mpeg2_vld_kernels[] = {
static struct media_kernel mpeg2_vld_kernels_gen4[] = {
{
"FRAME_INTRA",
FRAME_INTRA,
......@@ -280,7 +280,179 @@ static struct media_kernel mpeg2_vld_kernels[] = {
}
};
#define NUM_MPEG2_VLD_KERNELS (sizeof(mpeg2_vld_kernels)/sizeof(mpeg2_vld_kernels[0]))
/* On IGDNG */
static uint32_t frame_intra_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_intra.g4b.gen5"
};
static uint32_t frame_frame_pred_forward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_frame_pred_forward.g4b.gen5"
};
static uint32_t frame_frame_pred_backward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_frame_pred_backward.g4b.gen5"
};
static uint32_t frame_frame_pred_bidirect_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_frame_pred_bidirect.g4b.gen5"
};
static uint32_t frame_field_pred_forward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_field_pred_forward.g4b.gen5"
};
static uint32_t frame_field_pred_backward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_field_pred_backward.g4b.gen5"
};
static uint32_t frame_field_pred_bidirect_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/frame_field_pred_bidirect.g4b.gen5"
};
static uint32_t lib_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/lib.g4b.gen5"
};
/*field picture*/
static uint32_t field_intra_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_intra.g4b.gen5"
};
static uint32_t field_forward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_forward.g4b.gen5"
};
static uint32_t field_forward_16x8_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_forward_16x8.g4b.gen5"
};
static uint32_t field_backward_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_backward.g4b.gen5"
};
static uint32_t field_backward_16x8_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_backward_16x8.g4b.gen5"
};
static uint32_t field_bidirect_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_bidirect.g4b.gen5"
};
static uint32_t field_bidirect_16x8_kernel_gen5[][4] = {
#include "shaders/mpeg2/vld/field_bidirect_16x8.g4b.gen5"
};
static struct media_kernel mpeg2_vld_kernels_gen5[] = {
{
"FRAME_INTRA",
FRAME_INTRA,
frame_intra_kernel_gen5,
sizeof(frame_intra_kernel_gen5),
NULL
},
{
"FRAME_FRAME_PRED_FORWARD",
FRAME_FRAME_PRED_FORWARD,
frame_frame_pred_forward_kernel_gen5,
sizeof(frame_frame_pred_forward_kernel_gen5),
NULL
},
{
"FRAME_FRAME_PRED_BACKWARD",
FRAME_FRAME_PRED_BACKWARD,
frame_frame_pred_backward_kernel_gen5,
sizeof(frame_frame_pred_backward_kernel_gen5),
NULL
},
{
"FRAME_FRAME_PRED_BIDIRECT",
FRAME_FRAME_PRED_BIDIRECT,
frame_frame_pred_bidirect_kernel_gen5,
sizeof(frame_frame_pred_bidirect_kernel_gen5),
NULL
},
{
"FRAME_FIELD_PRED_FORWARD",
FRAME_FIELD_PRED_FORWARD,
frame_field_pred_forward_kernel_gen5,
sizeof(frame_field_pred_forward_kernel_gen5),
NULL
},
{
"FRAME_FIELD_PRED_BACKWARD",
FRAME_FIELD_PRED_BACKWARD,
frame_field_pred_backward_kernel_gen5,
sizeof(frame_field_pred_backward_kernel_gen5),
NULL
},
{
"FRAME_FIELD_PRED_BIDIRECT",
FRAME_FIELD_PRED_BIDIRECT,
frame_field_pred_bidirect_kernel_gen5,
sizeof(frame_field_pred_bidirect_kernel_gen5),
NULL
},
{
"LIB",
LIB_INTERFACE,
lib_kernel_gen5,
sizeof(lib_kernel_gen5),
NULL
},
{
"FIELD_INTRA",
FIELD_INTRA,
field_intra_kernel_gen5,
sizeof(field_intra_kernel_gen5),
NULL
},
{
"FIELD_FORWARD",
FIELD_FORWARD,
field_forward_kernel_gen5,
sizeof(field_forward_kernel_gen5),
NULL
},
{
"FIELD_FORWARD_16X8",
FIELD_FORWARD_16X8,
field_forward_16x8_kernel_gen5,
sizeof(field_forward_16x8_kernel_gen5),
NULL
},
{
"FIELD_BACKWARD",
FIELD_BACKWARD,
field_backward_kernel_gen5,
sizeof(field_backward_kernel_gen5),
NULL
},
{
"FIELD_BACKWARD_16X8",
FIELD_BACKWARD_16X8,
field_backward_16x8_kernel_gen5,
sizeof(field_backward_16x8_kernel_gen5),
NULL
},
{
"FIELD_BIDIRECT",
FIELD_BIDIRECT,
field_bidirect_kernel_gen5,
sizeof(field_bidirect_kernel_gen5),
NULL
},
{
"FIELD_BIDIRECT_16X8",
FIELD_BIDIRECT_16X8,
field_bidirect_16x8_kernel_gen5,
sizeof(field_bidirect_16x8_kernel_gen5),
NULL
}
};
static struct media_kernel *mpeg2_vld_kernels = NULL;
#define NUM_MPEG2_VLD_KERNELS (sizeof(mpeg2_vld_kernels_gen4)/sizeof(mpeg2_vld_kernels_gen4[0]))
static void
i965_media_mpeg2_surface_state(VADriverContextP ctx,
......@@ -747,8 +919,15 @@ i965_media_mpeg2_init(VADriverContextP ctx)
int i;
/* kernel */
assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) /
sizeof(mpeg2_vld_kernels_gen5[0])));
assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC);
if (IS_IGDNG(i965->intel.device_id))
mpeg2_vld_kernels = mpeg2_vld_kernels_gen5;
else
mpeg2_vld_kernels = mpeg2_vld_kernels_gen4;
for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
struct media_kernel *kernel = &mpeg2_vld_kernels[i];
kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
......
i965_drv_video/i965_render.c
View file @ 6310eeee
......@@ -74,6 +74,27 @@ static const unsigned int ps_subpic_kernel_static[][4] =
#include "shaders/render/exa_wm_write.g4b"
};
/* On IGDNG */
static const unsigned int sf_kernel_static_gen5[][4] =
{
#include "shaders/render/exa_sf.g4b.gen5"
};
static const unsigned int ps_kernel_static_gen5[][4] =
{
#include "shaders/render/exa_wm_xy.g4b.gen5"
#include "shaders/render/exa_wm_src_affine.g4b.gen5"
#include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
#include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
#include "shaders/render/exa_wm_write.g4b.gen5"
};
static const unsigned int ps_subpic_kernel_static_gen5[][4] =
{
#include "shaders/render/exa_wm_xy.g4b.gen5"
#include "shaders/render/exa_wm_src_affine.g4b.gen5"
#include "shaders/render/exa_wm_blend_subpicture.g4b.gen5"
#include "shaders/render/exa_wm_write.g4b.gen5"
};
static uint32_t float_to_uint (float f)
{
......@@ -99,7 +120,9 @@ struct render_kernel
const unsigned int (*bin)[4];
int size;
dri_bo *bo;
} render_kernels[] = {
};
static struct render_kernel render_kernels_gen4[] = {
{
"SF",
sf_kernel_static,
......@@ -121,7 +144,31 @@ struct render_kernel
}
};
#define NUM_RENDER_KERNEL (sizeof(render_kernels)/sizeof(render_kernels[0]))
static struct render_kernel render_kernels_gen5[] = {
{
"SF",
sf_kernel_static_gen5,
sizeof(sf_kernel_static_gen5),
NULL
},
{
"PS",
ps_kernel_static_gen5,
sizeof(ps_kernel_static_gen5),
NULL
},
{
"PS_SUBPIC",
ps_subpic_kernel_static_gen5,
sizeof(ps_subpic_kernel_static_gen5),
NULL
}
};
static struct render_kernel *render_kernels = NULL;
#define NUM_RENDER_KERNEL (sizeof(render_kernels_gen4)/sizeof(render_kernels_gen4[0]))
#define URB_VS_ENTRIES 8
#define URB_VS_ENTRY_SIZE 1
......@@ -150,7 +197,11 @@ i965_render_vs_unit(VADriverContextP ctx)
vs_state = render_state->vs.state->virtual;
memset(vs_state, 0, sizeof(*vs_state));
if (IS_IGDNG(i965->intel.device_id))
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
else
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
vs_state->vs6.vs_enable = 0;
vs_state->vs6.vert_cache_disable = 1;
......@@ -259,6 +310,10 @@ i965_subpic_render_wm_unit(VADriverContextP ctx)
wm_state->thread0.kernel_start_pointer = render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
wm_state->thread1.single_program_flow = 1; /* XXX */
if (IS_IGDNG(i965->intel.device_id))
wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
else
wm_state->thread1.binding_table_entry_count = 7;
wm_state->thread2.scratch_space_base_pointer = 0;
......@@ -272,6 +327,10 @@ i965_subpic_render_wm_unit(VADriverContextP ctx)
wm_state->wm4.stats_enable = 0;
wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
if (IS_IGDNG(i965->intel.device_id))
wm_state->wm4.sampler_count = 0; /* hardware requirement */
else
wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
......@@ -314,6 +373,10 @@ i965_render_wm_unit(VADriverContextP ctx)
wm_state->thread0.kernel_start_pointer = render_kernels[PS_KERNEL].bo->offset >> 6;
wm_state->thread1.single_program_flow = 1; /* XXX */
if (IS_IGDNG(i965->intel.device_id))
wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
else
wm_state->thread1.binding_table_entry_count = 7;
wm_state->thread2.scratch_space_base_pointer = 0;
......@@ -327,6 +390,10 @@ i965_render_wm_unit(VADriverContextP ctx)
wm_state->wm4.stats_enable = 0;
wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
if (IS_IGDNG(i965->intel.device_id))
wm_state->wm4.sampler_count = 0; /* hardware requirement */
else
wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
......@@ -903,6 +970,20 @@ i965_render_state_sip(VADriverContextP ctx)
static void
i965_render_state_base_address(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
if (IS_IGDNG(i965->intel.device_id)) {
BEGIN_BATCH(ctx, 8);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
} else {
BEGIN_BATCH(ctx, 6);
OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
......@@ -911,6 +992,7 @@ i965_render_state_base_address(VADriverContextP ctx)
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
ADVANCE_BATCH(ctx);
}
}
static void
......@@ -1026,6 +1108,31 @@ i965_render_drawing_rectangle(VADriverContextP ctx)
static void
i965_render_vertex_elements(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
if (IS_IGDNG(i965->intel.device_id)) {
BEGIN_BATCH(ctx, 5);
OUT_BATCH(ctx, CMD_VERTEX_ELEMENTS | 3);
/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(0 << VE0_OFFSET_SHIFT));
OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(8 << VE0_OFFSET_SHIFT));
OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
ADVANCE_BATCH(ctx);
} else {
BEGIN_BATCH(ctx, 5);
OUT_BATCH(ctx, CMD_VERTEX_ELEMENTS | 3);
/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
......@@ -1049,6 +1156,7 @@ i965_render_vertex_elements(VADriverContextP ctx)
(I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
ADVANCE_BATCH(ctx);
}
}
void
......@@ -1079,7 +1187,12 @@ i965_render_startup(VADriverContextP ctx)
VB0_VERTEXDATA |
((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
if (IS_IGDNG(i965->intel.device_id))
OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
else
OUT_BATCH(ctx, 3);
OUT_BATCH(ctx, 0);
OUT_BATCH(ctx,
......@@ -1270,6 +1383,14 @@ i965_render_init(VADriverContextP ctx)
int i;
/* kernel */
assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
sizeof(render_kernels_gen5[0])));
if (IS_IGDNG(i965->intel.device_id))
render_kernels = render_kernels_gen5;
else
render_kernels = render_kernels_gen4;
for (i = 0; i < NUM_RENDER_KERNEL; i++) {
struct render_kernel *kernel = &render_kernels[i];
kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
......
i965_drv_video/intel_driver.h
View file @ 6310eeee
......@@ -107,6 +107,9 @@ struct intel_region
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G41_G 0x2E32
#define PCI_CHIP_IGDNG_D_G 0x0042
#define PCI_CHIP_IGDNG_M_G 0x0046
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_G45_G || \
......@@ -114,4 +117,8 @@ struct intel_region
#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
#define IS_IGDNG_D(devid) (devid == PCI_CHIP_IGDNG_D_G)
#define IS_IGDNG_M(devid) (devid == PCI_CHIP_IGDNG_M_G)
#define IS_IGDNG(devid) (IS_IGDNG_D(devid) || IS_IGDNG_M(devid))
#endif /* _INTEL_DRIVER_H_ */
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