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libva
Commit 5b710431 authored by Austin Yuan's avatar Austin Yuan
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Merge branch 'master' of git+ssh://git.freedesktop.org/git/libva

parents ce998b14 9d7eddda
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Showing with 993 additions and 68 deletions
i965_drv_video/gen6_mfc.c
View file @ 5b710431
/*
* Copyright © 2010 Intel Corporation
* Copyright © 2010-2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
......@@ -43,7 +43,7 @@ gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
BEGIN_BCS_BATCH(batch,4);
BEGIN_BCS_BATCH(batch, 4);
OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
OUT_BCS_BATCH(batch,
......@@ -70,6 +70,42 @@ gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen
ADVANCE_BCS_BATCH(batch);
}
static void
gen7_mfc_pipe_mode_select(VADriverContextP ctx,
int standard_select,
struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
assert(standard_select == MFX_FORMAT_MPEG2 ||
standard_select == MFX_FORMAT_AVC);
BEGIN_BCS_BATCH(batch, 5);
OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
OUT_BCS_BATCH(batch,
(MFX_LONG_MODE << 17) | /* Must be long format for encoder */
(MFD_MODE_VLD << 15) | /* VLD mode */
(0 << 10) | /* disable Stream-Out */
(1 << 9) | /* Post Deblocking Output */
(0 << 8) | /* Pre Deblocking Output */
(0 << 5) | /* not in stitch mode */
(1 << 4) | /* encoding mode */
(standard_select << 0)); /* standard select: avc or mpeg2 */
OUT_BCS_BATCH(batch,
(0 << 7) | /* expand NOA bus flag */
(0 << 6) | /* disable slice-level clock gating */
(0 << 5) | /* disable clock gating for NOA */
(0 << 4) | /* terminate if AVC motion and POC table error occurs */
(0 << 3) | /* terminate if AVC mbdata error occurs */
(0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
(0 << 1) |
(0 << 0));
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
......@@ -98,6 +134,34 @@ gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_e
ADVANCE_BCS_BATCH(batch);
}
static void
gen7_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
BEGIN_BCS_BATCH(batch, 6);
OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch,
((mfc_context->surface_state.height - 1) << 18) |
((mfc_context->surface_state.width - 1) << 4));
OUT_BCS_BATCH(batch,
(MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
(1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
(0 << 22) | /* surface object control state, FIXME??? */
((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
(0 << 2) | /* must be 0 for interleave U/V */
(1 << 1) | /* must be tiled */
(I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
OUT_BCS_BATCH(batch,
(0 << 16) | /* must be 0 for interleave U/V */
(mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
OUT_BCS_BATCH(batch, 0);
ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
......@@ -166,6 +230,31 @@ gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_conte
ADVANCE_BCS_BATCH(batch);
}
static void
gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
BEGIN_BCS_BATCH(batch, 11);
OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
/* MFX Indirect MV Object Base Address */
OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
/*MFC Indirect PAK-BSE Object Base Address for Encoder*/
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
......@@ -238,6 +327,63 @@ gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_e
ADVANCE_BCS_BATCH(batch);
}
static void
gen7_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
BEGIN_BCS_BATCH(batch, 16);
OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
OUT_BCS_BATCH(batch,
((width_in_mbs * height_in_mbs) & 0xFFFF));
OUT_BCS_BATCH(batch,
((height_in_mbs - 1) << 16) |
((width_in_mbs - 1) << 0));
OUT_BCS_BATCH(batch,
(0 << 24) | /* Second Chroma QP Offset */
(0 << 16) | /* Chroma QP Offset */
(0 << 14) | /* Max-bit conformance Intra flag */
(0 << 13) | /* Max Macroblock size conformance Inter flag */
(0 << 12) | /* FIXME: Weighted_Pred_Flag */
(0 << 10) | /* FIXME: Weighted_BiPred_Idc */
(0 << 8) | /* FIXME: Image Structure */
(0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
OUT_BCS_BATCH(batch,
(0 << 16) | /* Mininum Frame size */
(0 << 15) | /* Disable reading of Macroblock Status Buffer */
(0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
(0 << 13) | /* CABAC 0 word insertion test enable */
(1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
(1 << 10) | /* Chroma Format IDC, 4:2:0 */
(0 << 9) | /* FIXME: MbMvFormatFlag */
(1 << 7) | /* 0:CAVLC encoding mode,1:CABAC */
(0 << 6) | /* Only valid for VLD decoding mode */
(0 << 5) | /* Constrained Intra Predition Flag, from PPS */
(0 << 4) | /* Direct 8x8 inference flag */
(0 << 3) | /* Only 8x8 IDCT Transform Mode Flag */
(1 << 2) | /* Frame MB only flag */
(0 << 1) | /* MBAFF mode is in active */
(0 << 0)); /* Field picture flag */
OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
(0xBB8 << 16) | /* InterMbMaxSz */
(0xEE8) ); /* IntraMbMaxSz */
OUT_BCS_BATCH(batch, 0); /* Reserved */
OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
OUT_BCS_BATCH(batch, 0x8C000000);
OUT_BCS_BATCH(batch, 0x00010000);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
......@@ -355,6 +501,82 @@ static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_con
ADVANCE_BCS_BATCH(batch);
}
static void
gen7_mfc_qm_state(VADriverContextP ctx,
int qm_type,
unsigned int *qm,
int qm_length,
struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int qm_buffer[16];
assert(qm_length <= 16);
assert(sizeof(*qm) == 4);
memcpy(qm_buffer, qm, qm_length * 4);
BEGIN_BCS_BATCH(batch, 18);
OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
OUT_BCS_BATCH(batch, qm_type << 0);
intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
ADVANCE_BCS_BATCH(batch);
}
static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
unsigned int qm[16] = {
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010
};
gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
}
static void
gen7_mfc_fqm_state(VADriverContextP ctx,
int fqm_type,
unsigned int *fqm,
int fqm_length,
struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int fqm_buffer[32];
assert(fqm_length <= 32);
assert(sizeof(*fqm) == 4);
memcpy(fqm_buffer, fqm, fqm_length * 4);
BEGIN_BCS_BATCH(batch, 34);
OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
OUT_BCS_BATCH(batch, fqm_type << 0);
intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
ADVANCE_BCS_BATCH(batch);
}
static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
unsigned int qm[32] = {
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000
};
gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
}
static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
......@@ -373,7 +595,6 @@ static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder
ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
{
......@@ -535,6 +756,7 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
struct encode_state *encode_state,
struct gen6_encoder_context *gen6_encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
......@@ -561,18 +783,32 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
if (emit_new_state) {
intel_batchbuffer_emit_mi_flush(batch);
gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
gen6_mfc_surface_state(ctx, gen6_encoder_context);
if (IS_GEN7(i965->intel.device_id)) {
gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
gen7_mfc_surface_state(ctx, gen6_encoder_context);
gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
} else {
gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
gen6_mfc_surface_state(ctx, gen6_encoder_context);
gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
}
gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
if (IS_GEN7(i965->intel.device_id)) {
gen7_mfc_avc_img_state(ctx, gen6_encoder_context);
gen7_mfc_avc_qm_state(ctx, gen6_encoder_context);
gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context);
} else {
gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
}
gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
/*gen6_mfc_avc_directmode_state(ctx);*/
gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context);
/*gen6_mfc_avc_insert_object(ctx, 0);*/
emit_new_state = 0;
}
......
i965_drv_video/gen6_vme.c
View file @ 5b710431
/*
* Copyright © 2009 Intel Corporation
* Copyright © 2010-2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
......@@ -40,11 +40,17 @@
#include "gen6_vme.h"
#include "i965_encoder.h"
#define SURFACE_STATE_PADDED_SIZE_0 ALIGN(sizeof(struct i965_surface_state), 32)
#define SURFACE_STATE_PADDED_SIZE_1 ALIGN(sizeof(struct i965_surface_state2), 32)
#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_0, SURFACE_STATE_PADDED_SIZE_1)
#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
#define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6)
#define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
#define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
#define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
#define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32)
#define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32)
#define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN7)
#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
#define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6)
#define VME_INTRA_SHADER 0
#define VME_INTER_SHADER 1
......@@ -55,12 +61,10 @@
static const uint32_t gen6_vme_intra_frame[][4] = {
#include "shaders/vme/intra_frame.g6b"
{0,0,0,0}
};
static const uint32_t gen6_vme_inter_frame[][4] = {
#include "shaders/vme/inter_frame.g6b"
{0,0,0,0}
};
static struct i965_kernel gen6_vme_kernels[] = {
......@@ -80,6 +84,31 @@ static struct i965_kernel gen6_vme_kernels[] = {
}
};
static const uint32_t gen7_vme_intra_frame[][4] = {
#include "shaders/vme/intra_frame.g7b"
};
static const uint32_t gen7_vme_inter_frame[][4] = {
#include "shaders/vme/inter_frame.g7b"
};
static struct i965_kernel gen7_vme_kernels[] = {
{
"VME Intra Frame",
VME_INTRA_SHADER, /*index*/
gen7_vme_intra_frame,
sizeof(gen7_vme_intra_frame),
NULL
},
{
"VME inter Frame",
VME_INTER_SHADER,
gen7_vme_inter_frame,
sizeof(gen7_vme_inter_frame),
NULL
}
};
static void
gen6_vme_set_common_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
{
......@@ -308,6 +337,246 @@ static VAStatus gen6_vme_surface_setup(VADriverContextP ctx,
return VA_STATUS_SUCCESS;
}
/*
* Surface state for IvyBridge
*/
static void
gen7_vme_set_common_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
{
switch (tiling) {
case I915_TILING_NONE:
ss->ss0.tiled_surface = 0;
ss->ss0.tile_walk = 0;
break;
case I915_TILING_X:
ss->ss0.tiled_surface = 1;
ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
break;
case I915_TILING_Y:
ss->ss0.tiled_surface = 1;
ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
break;
}
}
static void
gen7_vme_set_source_surface_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
{
switch (tiling) {
case I915_TILING_NONE:
ss->ss2.tiled_surface = 0;
ss->ss2.tile_walk = 0;
break;
case I915_TILING_X:
ss->ss2.tiled_surface = 1;
ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
break;
case I915_TILING_Y:
ss->ss2.tiled_surface = 1;
ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
break;
}
}
/* only used for VME source surface state */
static void gen7_vme_source_surface_state(VADriverContextP ctx,
int index,
struct object_surface *obj_surface,
struct gen6_encoder_context *gen6_encoder_context)
{
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
struct gen7_surface_state2 *ss;
dri_bo *bo;
int w, h, w_pitch, h_pitch;
unsigned int tiling, swizzle;
assert(obj_surface->bo);
w = obj_surface->orig_width;
h = obj_surface->orig_height;
w_pitch = obj_surface->width;
h_pitch = obj_surface->height;
bo = vme_context->surface_state_binding_table.bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
ss = (struct gen7_surface_state2 *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
memset(ss, 0, sizeof(*ss));
ss->ss0.surface_base_address = obj_surface->bo->offset;
ss->ss1.cbcr_pixel_offset_v_direction = 2;
ss->ss1.width = w - 1;
ss->ss1.height = h - 1;
ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
ss->ss2.interleave_chroma = 1;
ss->ss2.pitch = w_pitch - 1;
ss->ss2.half_pitch_for_chroma = 0;
dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
gen7_vme_set_source_surface_tiling(ss, tiling);
/* UV offset for interleave mode */
ss->ss3.x_offset_for_cb = 0;
ss->ss3.y_offset_for_cb = h_pitch;
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_RENDER, 0,
0,
SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
obj_surface->bo);
((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
dri_bo_unmap(bo);
}
static void
gen7_vme_media_source_surface_state(VADriverContextP ctx,
int index,
struct object_surface *obj_surface,
struct gen6_encoder_context *gen6_encoder_context)
{
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
struct gen7_surface_state *ss;
dri_bo *bo;
int w, h, w_pitch;
unsigned int tiling, swizzle;
/* Y plane */
w = obj_surface->orig_width;
h = obj_surface->orig_height;
w_pitch = obj_surface->width;
bo = vme_context->surface_state_binding_table.bo;
dri_bo_map(bo, True);
assert(bo->virtual);
ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
memset(ss, 0, sizeof(*ss));
ss->ss0.surface_type = I965_SURFACE_2D;
ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
ss->ss1.base_addr = obj_surface->bo->offset;
ss->ss2.width = w / 4 - 1;
ss->ss2.height = h - 1;
ss->ss3.pitch = w_pitch - 1;
dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
gen7_vme_set_common_surface_tiling(ss, tiling);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_RENDER, 0,
0,
SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
obj_surface->bo);
((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
dri_bo_unmap(bo);
}
static VAStatus
gen7_vme_output_buffer_setup(VADriverContextP ctx,
struct encode_state *encode_state,
int index,
struct gen6_encoder_context *gen6_encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
struct gen7_surface_state *ss;
dri_bo *bo;
VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
int is_intra = pSliceParameter->slice_flags.bits.is_intra;
int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
int num_entries;
if ( is_intra ) {
vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
} else {
vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs * 4;
}
vme_context->vme_output.size_block = 16; /* an OWORD */
vme_context->vme_output.pitch = ALIGN(vme_context->vme_output.size_block, 16);
bo = dri_bo_alloc(i965->intel.bufmgr,
"VME output buffer",
vme_context->vme_output.num_blocks * vme_context->vme_output.pitch,
0x1000);
assert(bo);
vme_context->vme_output.bo = bo;
bo = vme_context->surface_state_binding_table.bo;
dri_bo_map(bo, 1);
assert(bo->virtual);
ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
ss = bo->virtual;
memset(ss, 0, sizeof(*ss));
/* always use 16 bytes as pitch on Sandy Bridge */
num_entries = vme_context->vme_output.num_blocks * vme_context->vme_output.pitch / 16;
ss->ss0.surface_type = I965_SURFACE_BUFFER;
ss->ss1.base_addr = vme_context->vme_output.bo->offset;
ss->ss2.width = ((num_entries - 1) & 0x7f);
ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
ss->ss3.pitch = vme_context->vme_output.pitch - 1;
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0,
SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
vme_context->vme_output.bo);
((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
dri_bo_unmap(bo);
return VA_STATUS_SUCCESS;
}
static VAStatus gen7_vme_surface_setup(VADriverContextP ctx,
struct encode_state *encode_state,
int is_intra,
struct gen6_encoder_context *gen6_encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct object_surface *obj_surface;
VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
/*Setup surfaces state*/
/* current picture for encoding */
obj_surface = SURFACE(encode_state->current_render_target);
assert(obj_surface);
gen7_vme_source_surface_state(ctx, 1, obj_surface, gen6_encoder_context);
gen7_vme_media_source_surface_state(ctx, 4, obj_surface, gen6_encoder_context);
if ( ! is_intra ) {
/* reference 0 */
obj_surface = SURFACE(pPicParameter->reference_picture);
assert(obj_surface);
gen7_vme_source_surface_state(ctx, 2, obj_surface, gen6_encoder_context);
/* reference 1, FIXME: */
// obj_surface = SURFACE(pPicParameter->reference_picture);
// assert(obj_surface);
//gen7_vme_source_surface_state(ctx, 3, obj_surface);
}
/* VME output */
gen7_vme_output_buffer_setup(ctx, encode_state, 0, gen6_encoder_context);
return VA_STATUS_SUCCESS;
}
static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
struct encode_state *encode_state,
struct gen6_encoder_context *gen6_encoder_context)
......@@ -627,12 +896,17 @@ static VAStatus gen6_vme_prepare(VADriverContextP ctx,
struct encode_state *encode_state,
struct gen6_encoder_context *gen6_encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
VAStatus vaStatus = VA_STATUS_SUCCESS;
VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
int is_intra = pSliceParameter->slice_flags.bits.is_intra;
/*Setup all the memory object*/
gen6_vme_surface_setup(ctx, encode_state, is_intra, gen6_encoder_context);
if (IS_GEN7(i965->intel.device_id))
gen7_vme_surface_setup(ctx, encode_state, is_intra, gen6_encoder_context);
else
gen6_vme_surface_setup(ctx, encode_state, is_intra, gen6_encoder_context);
gen6_vme_interface_setup(ctx, encode_state, gen6_encoder_context);
gen6_vme_constant_setup(ctx, encode_state, gen6_encoder_context);
gen6_vme_vme_state_setup(ctx, encode_state, is_intra, gen6_encoder_context);
......@@ -679,7 +953,10 @@ Bool gen6_vme_context_init(VADriverContextP ctx, struct gen6_vme_context *vme_co
struct i965_driver_data *i965 = i965_driver_data(ctx);
int i;
memcpy(vme_context->vme_kernels, gen6_vme_kernels, sizeof(vme_context->vme_kernels));
if (IS_GEN7(i965->intel.device_id))
memcpy(vme_context->vme_kernels, gen7_vme_kernels, sizeof(vme_context->vme_kernels));
else
memcpy(vme_context->vme_kernels, gen6_vme_kernels, sizeof(vme_context->vme_kernels));
for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
/*Load kernel into GPU memory*/
......
i965_drv_video/i965_defines.h
View file @ 5b710431
......@@ -283,6 +283,7 @@
#define MFX_AES_STATE MFX(2, 0, 0, 5)
#define MFX_STATE_POINTER MFX(2, 0, 0, 6)
#define MFX_QM_STATE MFX(2, 0, 0, 7)
#define MFX_FQM_STATE MFX(2, 0, 0, 8)
#define MFX_WAIT MFX(1, 0, 0, 0)
......
i965_drv_video/i965_drv_video.c
View file @ 5b710431
......@@ -158,7 +158,7 @@ static struct hw_codec_info gen6_hw_codec_info = {
extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, VAProfile);
static struct hw_codec_info gen7_hw_codec_info = {
.dec_hw_context_init = gen7_dec_hw_context_init,
.enc_hw_context_init = NULL,
.enc_hw_context_init = gen6_enc_hw_context_init,
};
VAStatus
......
i965_drv_video/i965_structs.h
View file @ 5b710431
......@@ -1252,4 +1252,56 @@ struct gen7_sampler_state
} ss3;
};
struct gen7_surface_state2
{
struct {
unsigned int surface_base_address;
} ss0;
struct {
unsigned int cbcr_pixel_offset_v_direction:2;
unsigned int picture_structure:2;
unsigned int width:14;
unsigned int height:14;
} ss1;
struct {
unsigned int tile_walk:1;
unsigned int tiled_surface:1;
unsigned int half_pitch_for_chroma:1;
unsigned int pitch:18;
unsigned int pad0:1;
unsigned int surface_object_control_data:4;
unsigned int pad1:1;
unsigned int interleave_chroma:1;
unsigned int surface_format:4;
} ss2;
struct {
unsigned int y_offset_for_cb:15;
unsigned int pad0:1;
unsigned int x_offset_for_cb:14;
unsigned int pad1:2;
} ss3;
struct {
unsigned int y_offset_for_cr:15;
unsigned int pad0:1;
unsigned int x_offset_for_cr:14;
unsigned int pad1:2;
} ss4;
struct {
unsigned int pad0;
} ss5;
struct {
unsigned int pad0;
} ss6;
struct {
unsigned int pad0;
} ss7;
};
#endif /* _I965_STRUCTS_H_ */
i965_drv_video/intel_batchbuffer.c
View file @ 5b710431
......@@ -166,10 +166,19 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
if (batch->flag == I915_EXEC_RENDER) {
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_PIPE_CONTROL | 0x2);
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
if (IS_GEN6(intel->device_id))
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
else
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_DC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
ADVANCE_BATCH(batch);
......
i965_drv_video/intel_driver.h
View file @ 5b710431
......@@ -50,6 +50,7 @@
#define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
#define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
#define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
#define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
#define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
#define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
......
i965_drv_video/shaders/vme/Makefile.am
View file @ 5b710431
VME_CORE = intra_frame.asm inter_frame.asm
INTEL_G6B = intra_frame.g6b inter_frame.g6b
INTEL_INC = vme_header.inc
INTEL_G6A = intra_frame.g6a inter_frame.g6a
INTEL_INC = gen6_vme_header.inc
INTEL_G7B = intra_frame.g7b inter_frame.g7b
INTEL_G7A = intra_frame.g7a inter_frame.g7a
INTEL_INC_GEN7 = gen7_vme_header.inc
EXTRA_DIST = $(INTEL_G6B) \
$(INTEL_INC)
$(INTEL_G6A) \
$(INTEL_INC) \
$(INTEL_G7B) \
$(INTEL_G7A) \
$(INTEL_INC_GEN7)
if HAVE_GEN4ASM
SUFFIXES = .asm .g6b
.asm.g6b:
m4 $*.asm > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
SUFFIXES = .g6a .g6b .g7a .g7b
.g6a.g6b:
m4 $*.g6a > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
.g7a.g7b:
m4 $*.g7a > $*.g7m && intel-gen4asm -g 7 -o $@ $*.g7m && rm $*.g7m
$(INTEL_G6B): $(INTEL_INC) $(VME_CORE)
$(INTEL_G6B): $(INTEL_INC)
$(INTEL_G7B): $(INTEL_INC_GEN7) $(VME_CORE)
BUILT_SOURCES= $(INTEL_G6B)
BUILT_SOURCES= $(INTEL_G6B) $(INTEL_G7B)
clean-local:
-rm -f $(INTEL_G6B)
-rm -f $(INTEL_G7B)
endif
i965_drv_video/shaders/vme/vme_header.inc → i965_drv_video/shaders/vme/gen6_vme_header.inc
View file @ 5b710431
......@@ -46,16 +46,31 @@ define(`INTER_SAD_HAAR', `0x00200000')
define(`INTRA_SAD_NONE', `0x00000000')
define(`INTRA_SAD_HAAR', `0x00800000')
define(`INTER_PART_MASK', `0x7E000000')
define(`INTER_PART_MASK', `0x7E000000')
define(`REF_REGION_SIZE', `0x2020:UW')
define(`BI_SUB_MB_PART_MASK', `0x0c000000')
define(`MAX_NUM_MV', `0x00000020')
define(`SEARCH_PATH_LEN', `0x00003F3F')
define(`SEARCH_PATH_LEN', `0x00003F3F')
define(`INTRA_PREDICTORE_MODE', `0x11111111:UD')
define(`OBW_CACHE_TYPE', `5')
define(`OBW_MESSAGE_TYPE', `8')
define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT')
define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */
define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */
define(`OBW_CONTROL_2', `2') /* 2 OWords */
define(`OBW_CONTROL_3', `3') /* 4 OWords */
define(`OBW_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */
define(`OBW_HEADER_PRESENT', `1')
/* GRF registers
* r0 header
* r1~r4 constant buffer (reserved)
......@@ -99,6 +114,7 @@ define(`vme_wb3', `r15')
* GRF 16 -- write back for Oword Block Write message with write commit bit
*/
define(`obw_wb', `r16')
define(`obw_wb_length', `1')
/*
* GRF 18~21 -- Intra Neighbor Edge Pixels
......@@ -121,12 +137,24 @@ define(`tmp_reg3', `r35')
/*
* MRF registers
*/
define(`msg_ind', `0')
define(`msg_reg0', `m0') /* m0 */
define(`msg_reg1', `m1') /* m1 */
define(`msg_reg2', `m2') /* m2 */
define(`msg_reg3', `m3') /* m3 */
define(`msg_reg4', `m4') /* m4 */
/*
* VME message payload
*/
define(`vme_msg_length', `4')
define(`vme_intra_wb_length', `1')
define(`vme_inter_wb_length', `4')
define(`vme_msg_ind', `msg_ind')
define(`vme_msg_0', `msg_reg0')
define(`vme_msg_1', `msg_reg1')
define(`vme_msg_2', `msg_reg2')
define(`vme_msg_3', `vme_msg_2')
define(`vme_msg_4', `msg_reg3')
i965_drv_video/shaders/vme/gen7_vme_header.inc 0 → 100644
View file @ 5b710431
/*
* Copyright © <2010>, Intel Corporation.
*
* This program is licensed under the terms and conditions of the
* Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
* http://www.opensource.org/licenses/eclipse-1.0.php.
*
*/
// Modual name: ME_header.inc
//
// Global symbols define
//
/*
* Constant
*/
define(`VME_MESSAGE_TYPE_INTER', `1')
define(`VME_MESSAGE_TYPE_INTRA', `2')
define(`VME_MESSAGE_TYPE_MIXED', `3')
define(`BLOCK_32X1', `0x0000001F')
define(`BLOCK_4X16', `0x000F0003')
define(`LUMA_INTRA_16x16_DISABLE', `0x1')
define(`LUMA_INTRA_8x8_DISABLE', `0x2')
define(`LUMA_INTRA_4x4_DISABLE', `0x4')
define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60')
define(`INTRA_PRED_AVAIL_FLAG_B', `0x10')
define(`INTRA_PRED_AVAIL_FLAG_C', `0x8')
define(`INTRA_PRED_AVAIL_FLAG_D', `0x4')
define(`BIND_IDX_VME', `1')
define(`BIND_IDX_VME_REF0', `2')
define(`BIND_IDX_VME_REF1', `3')
define(`BIND_IDX_OUTPUT', `0')
define(`BIND_IDX_INEP', `4')
define(`SUB_PEL_MODE_INTEGER', `0x00000000')
define(`SUB_PEL_MODE_HALF', `0x00001000')
define(`SUB_PEL_MODE_QUARTER', `0x00003000')
define(`INTER_SAD_NONE', `0x00000000')
define(`INTER_SAD_HAAR', `0x00200000')
define(`INTRA_SAD_NONE', `0x00000000')
define(`INTRA_SAD_HAAR', `0x00800000')
define(`INTER_PART_MASK', `0x7E000000')
define(`REF_REGION_SIZE', `0x2020:UW')
define(`BI_SUB_MB_PART_MASK', `0x0c000000')
define(`MAX_NUM_MV', `0x00000020')
define(`SEARCH_PATH_LEN', `0x00003F3F')
define(`INTRA_PREDICTORE_MODE', `0x11111111:UD')
define(`OBW_CACHE_TYPE', `10')
define(`OBW_MESSAGE_TYPE', `8')
define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT')
define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */
define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */
define(`OBW_CONTROL_2', `2') /* 2 OWords */
define(`OBW_CONTROL_3', `3') /* 4 OWords */
define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */
define(`OBW_HEADER_PRESENT', `1')
/* GRF registers
* r0 header
* r1~r4 constant buffer (reserved)
* r5 inline data
* r6~r11 reserved
* r12 write back of VME message
* r13 write back of Oword Block Write
*/
/*
* GRF 0 -- header
*/
define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */
/*
* GRF 1~4 -- Constant Buffer (reserved)
*/
/*
* GRF 5 -- inline data
*/
define(`inline_reg0', `r5')
define(`w_in_mb_uw', `inline_reg0.2')
define(`orig_xy_ub', `inline_reg0.0')
define(`orig_x_ub', `inline_reg0.0') /* in macroblock */
define(`orig_y_ub', `inline_reg0.1')
/*
* GRF 6~11 -- reserved
*/
/*
* GRF 12~15 -- write back for VME message
*/
define(`vme_wb', `r12')
define(`vme_wb0', `r12')
define(`vme_wb1', `r13')
define(`vme_wb2', `r14')
define(`vme_wb3', `r15')
/*
* GRF 16 -- reserved
*/
/*
* write commit is removed on Ivybridge
*/
define(`obw_wb', `null<1>:W')
define(`obw_wb_length', `0')
/*
* GRF 18~21 -- Intra Neighbor Edge Pixels
*/
define(`INEP_ROW', `r18')
define(`INEP_COL0', `r20')
define(`INEP_COL1', `r21')
/*
* temporary registers
*/
define(`tmp_reg0', `r32')
define(`tmp_reg1', `r33')
define(`intra_part_mask_ub', `tmp_reg1.28')
define(`mb_intra_struct_ub', `tmp_reg1.29')
define(`tmp_reg2', `r34')
define(`tmp_x_w', `tmp_reg2.0')
define(`tmp_reg3', `r35')
/*
* Message Payload registers
*/
define(`msg_ind', `64')
define(`msg_reg0', `g64')
define(`msg_reg1', `g65')
define(`msg_reg2', `g66')
define(`msg_reg3', `g67')
define(`msg_reg4', `g68')
/*
* VME message payload
*/
define(`vme_msg_length', `5')
define(`vme_intra_wb_length', `1')
define(`vme_inter_wb_length', `6')
define(`vme_msg_ind', `msg_ind')
define(`vme_msg_0', `msg_reg0')
define(`vme_msg_1', `msg_reg1')
define(`vme_msg_2', `msg_reg2')
define(`vme_msg_3', `msg_reg3')
define(`vme_msg_4', `msg_reg4')
i965_drv_video/shaders/vme/inter_frame.asm
View file @ 5b710431
......@@ -15,8 +15,6 @@
// Now, begin source code....
//
include(`vme_header.inc')
/*
* __START
*/
......@@ -30,27 +28,42 @@ mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
/* m0 */
mul (2) tmp_reg0.8<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* Source = (x, y) * 16 */
mul (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1};
add (2) tmp_reg0.0<1>:W tmp_reg0.0<2,2,1>:W -8:W {align1}; /* Reference = (x-8,y-8)-(x+24,y+24) */
add (2) tmp_reg0.0<1>:W tmp_reg0.0<2,2,1>:W -8:W {align1}; /* Reference = (x-8,y-8)-(x+24,y+24) */
mov (1) tmp_reg0.12<1>:UD INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
mov (1) tmp_reg0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 32x32 */
mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
mov (8) vme_msg_0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
/* m1 */
mov (1) tmp_reg1.4<1>:UD MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */
mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1};
mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1};
mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
mov (8) vme_msg_1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
/* m2 */
mov (8) msg_reg2<1>:UD 0x0:UD {align1};
mov (8) vme_msg_2<1>:UD 0x0:UD {align1};
/* m3 */
mov (8) msg_reg3<1>:UD 0x0:UD {align1};
mov (8) vme_msg_3<1>:UD 0x0:UD {align1};
send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTER) mlen 4 rlen 4 {align1};
/* m4 */
mov (8) vme_msg_4<1>:UD 0x0:UD {align1};
send (8)
vme_msg_ind
vme_wb
null
vme(
BIND_IDX_VME,
0,
0,
VME_MESSAGE_TYPE_INTER
)
mlen vme_msg_length
rlen vme_inter_wb_length
{align1};
/*
* Oword Block Write message
*/
......@@ -61,17 +74,31 @@ mov (1) tmp_reg3.20<1>:UB thread_id_ub {align1}; /* dispa
mov (8) msg_reg0.0<1>:UD tmp_reg3.0<8,8,1>:UD {align1};
mov (2) tmp_reg3.0<1>:UW vme_wb1.0<2,2,1>:UB {align1};
add (2) tmp_reg3.0<1>:W tmp_reg3.0<16,16,1>:W -32:W {align1};
add (2) tmp_reg3.0<1>:W tmp_reg3.0<2,2,1>:W -32:W {align1};
mov (8) msg_reg1.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1};
mov (8) msg_reg2.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1};
/* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */
send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 3, 8, 1) mlen 3 rlen 1 {align1};
send (16)
msg_ind
obw_wb
null
data_port(
OBW_CACHE_TYPE,
OBW_MESSAGE_TYPE,
OBW_CONTROL_3,
OBW_BIND_IDX,
OBW_WRITE_COMMIT_CATEGORY,
OBW_HEADER_PRESENT
)
mlen 3
rlen obw_wb_length
{align1};
/*
* kill thread
*/
mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1};
send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
i965_drv_video/shaders/vme/inter_frame.g6a 0 → 100644
View file @ 5b710431
include(`gen6_vme_header.inc')
include(`inter_frame.asm')
i965_drv_video/shaders/vme/inter_frame.g6b
View file @ 5b710431
......@@ -11,6 +11,7 @@
{ 0x00000001, 0x24280061, 0x00000000, 0x00003f3f },
{ 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x20400062, 0x00000000, 0x00000000 },
{ 0x00600001, 0x20400062, 0x00000000, 0x00000000 },
{ 0x00600001, 0x20600062, 0x00000000, 0x00000000 },
{ 0x08600031, 0x21801cdd, 0x00000000, 0x08482000 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
......@@ -19,7 +20,7 @@
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
{ 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
{ 0x00200040, 0x24603dad, 0x00b10460, 0xffe0ffe0 },
{ 0x00200040, 0x24603dad, 0x00450460, 0xffe0ffe0 },
{ 0x00600001, 0x20200022, 0x008c0460, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008c0460, 0x00000000 },
{ 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 },
......
i965_drv_video/shaders/vme/inter_frame.g7a 0 → 100644
View file @ 5b710431
include(`gen7_vme_header.inc')
include(`inter_frame.asm')
i965_drv_video/shaders/vme/inter_frame.g7b 0 → 100644
View file @ 5b710431
{ 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
{ 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
{ 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
{ 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 },
{ 0x00200040, 0x24003dad, 0x00450400, 0xfff8fff8 },
{ 0x00000001, 0x240c0061, 0x00000000, 0x7e203000 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00000001, 0x24160169, 0x00000000, 0x20202020 },
{ 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
{ 0x00000001, 0x24240061, 0x00000000, 0x00000020 },
{ 0x00000001, 0x24280061, 0x00000000, 0x00003f3f },
{ 0x00600001, 0x28200021, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x28600061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x28800061, 0x00000000, 0x00000000 },
{ 0x08600031, 0x21801cbd, 0x00000800, 0x0a682001 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
{ 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
{ 0x00000041, 0x24680c21, 0x00000468, 0x00000004 },
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0460, 0x00000000 },
{ 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
{ 0x00200040, 0x24603dad, 0x00450460, 0xffe0ffe0 },
{ 0x00600001, 0x28200021, 0x008c0460, 0x00000000 },
{ 0x00600001, 0x28400021, 0x008c0460, 0x00000000 },
{ 0x0a800031, 0x20001cac, 0x00000800, 0x060a0300 },
{ 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
{ 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 },
i965_drv_video/shaders/vme/intra_frame.asm
View file @ 5b710431
......@@ -15,8 +15,6 @@
// Now, begin source code....
//
include(`vme_header.inc')
/*
* __START
*/
......@@ -34,7 +32,7 @@ add (1) tmp_reg0.4<1>:D tmp_reg0.4<0,1,0>:D -1:W {align1}; /* Y offs
mov (1) tmp_reg0.8<1>:UD BLOCK_32X1 {align1};
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
/* COL */
mul (2) tmp_reg0.0<1>:D orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
......@@ -42,7 +40,7 @@ add (1) tmp_reg0.0<1>:D tmp_reg0.0<0,1,0>:D -4:W {align1}; /* X offs
mov (1) tmp_reg0.8<1>:UD BLOCK_4X16 {align1};
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
/*
* VME message
......@@ -50,7 +48,7 @@ send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
/* m0 */
mul (2) tmp_reg0.8<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
mov (8) vme_msg_0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
/* m1 */
mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
......@@ -69,16 +67,32 @@ add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};
mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */
(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */
mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
mov (8) vme_msg_1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
/* m2 */
mov (8) msg_reg2<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
mov (8) vme_msg_2<1>:UD 0x0:UD {align1};
/* m3 */
mov (8) msg_reg3<1>:UD 0x0 {align1};
mov (16) msg_reg3.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
mov (1) msg_reg3.16<1>:UD INTRA_PREDICTORE_MODE {align1};
send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTRA) mlen 4 rlen 1 {align1};
mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
/* m4 */
mov (8) vme_msg_4<1>:UD 0x0 {align1};
mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1};
send (8)
vme_msg_ind
vme_wb
null
vme(
BIND_IDX_VME,
0,
0,
VME_MESSAGE_TYPE_INTRA
)
mlen vme_msg_length
rlen vme_intra_wb_length
{align1};
/*
* Oword Block Write message
......@@ -93,10 +107,24 @@ mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1};
mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1};
mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1};
/* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 0, 8, 1) mlen 2 rlen 1 {align1};
send (16)
msg_ind
obw_wb
null
data_port(
OBW_CACHE_TYPE,
OBW_MESSAGE_TYPE,
OBW_CONTROL_0,
OBW_BIND_IDX,
OBW_WRITE_COMMIT_CATEGORY,
OBW_HEADER_PRESENT
)
mlen 2
rlen obw_wb_length
{align1};
/*
* kill thread
*/
mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1};
send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
i965_drv_video/shaders/vme/intra_frame.g6a 0 → 100644
View file @ 5b710431
include(`gen6_vme_header.inc')
include(`intra_frame.asm')
i965_drv_video/shaders/vme/intra_frame.g6b
View file @ 5b710431
......@@ -6,13 +6,13 @@
{ 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x04800031, 0x22401cdd, 0x00000000, 0x02188004 },
{ 0x04600031, 0x22401cd1, 0x00000000, 0x02188004 },
{ 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
{ 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc },
{ 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x04800031, 0x22801cdd, 0x00000000, 0x02288004 },
{ 0x04600031, 0x22801cd1, 0x00000000, 0x02288004 },
{ 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
......@@ -28,6 +28,7 @@
{ 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 },
{ 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x20400062, 0x00000000, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x206000e2, 0x00000000, 0x00000000 },
{ 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 },
......
i965_drv_video/shaders/vme/intra_frame.g7a 0 → 100644
View file @ 5b710431
include(`gen7_vme_header.inc')
include(`intra_frame.asm')
i965_drv_video/shaders/vme/intra_frame.g7b 0 → 100644
View file @ 5b710431
{ 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
{ 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
{ 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
{ 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
{ 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
{ 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
{ 0x04600031, 0x22401cb1, 0x00000800, 0x02190004 },
{ 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
{ 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc },
{ 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
{ 0x04600031, 0x22801cb1, 0x00000800, 0x02290004 },
{ 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
{ 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
{ 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
{ 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000010 },
{ 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000004 },
{ 0x00000040, 0x24402e2d, 0x000000a0, 0x00010001 },
{ 0x00000040, 0x2440352d, 0x000000a2, 0x00004440 },
{ 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 },
{ 0x00600001, 0x28200021, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x28600021, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x288000e1, 0x00000000, 0x00000000 },
{ 0x00800001, 0x28800231, 0x00cf0283, 0x00000000 },
{ 0x00000001, 0x28900061, 0x00000000, 0x11111111 },
{ 0x08600031, 0x21801cbd, 0x00000800, 0x0a184001 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
{ 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0460, 0x00000000 },
{ 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
{ 0x00000001, 0x28240021, 0x00000190, 0x00000000 },
{ 0x00000001, 0x28280021, 0x00000194, 0x00000000 },
{ 0x00000001, 0x282c0021, 0x00000198, 0x00000000 },
{ 0x0a800031, 0x20001cac, 0x00000800, 0x040a0000 },
{ 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
{ 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 },
test/encode/avcenc.c
View file @ 5b710431
......@@ -16,7 +16,6 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <pciaccess.h>
#include <assert.h>
#include <time.h>
......
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