omap2 clock: fix CodingStyle issues

Clean up some CodingStyle non-conformances in clock.c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/clock.c

@@ -396,7 +396,7 @@ static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 	if (div_array == NULL)
 		return ~1;
 
-	for (i=0; i < size; i++) {
+	for (i = 0; i < size; i++) {
 		test_rate = src_rate / *div_array;
 		if (test_rate <= tgt_rate)
 			return *div_array;
@@ -418,37 +418,37 @@ static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 	u32 gfx_div[] = {2, 3, 4};
 	u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 	u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
-	u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
+	u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 	u32 best_div = ~0, asize = 0;
 	u32 *div_array = NULL;
 
 	switch (tclk->flags & SRC_RATE_SEL_MASK) {
 	case CM_GFX_SEL1:
-		asize = 3;
+		asize = ARRAY_SIZE(gfx_div);
 		div_array = gfx_div;
 		break;
 	case CM_PLL_SEL1:
 		return omap2_dpll_round_rate(target_rate);
 	case CM_SYSCLKOUT_SEL1:
-		asize = 5;
+		asize = ARRAY_SIZE(sysclkout_div);
 		div_array = sysclkout_div;
 		break;
 	case CM_CORE_SEL1:
-		if(tclk == &dss1_fck){
-			if(tclk->parent == &core_ck){
-				asize = 10;
+		if (tclk == &dss1_fck) {
+			if (tclk->parent == &core_ck) {
+				asize = ARRAY_SIZE(dss1_div);
 				div_array = dss1_div;
 			} else {
 				*new_div = 0; /* fixed clk */
 				return(tclk->parent->rate);
 			}
-		} else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
-			if(tclk->parent == &core_ck){
-				asize = 10;
-				div_array = vylnq_div;
+		} else if ((tclk == &vlynq_fck) && cpu_is_omap2420()) {
+			if (tclk->parent == &core_ck) {
+				asize = ARRAY_SIZE(vlynq_div);
+				div_array = vlynq_div;
 			} else {
 				*new_div = 0; /* fixed clk */
-				return(tclk->parent->rate);
+				return (tclk->parent->rate);
 			}
 		}
 		break;
@@ -456,7 +456,7 @@ static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 
 	best_div = omap2_divider_from_table(asize, div_array,
 					    tclk->parent->rate, target_rate);
-	if (best_div == ~0){
+	if (best_div == ~0) {
 		*new_div = 1;
 		return best_div; /* signal error */
 	}
@@ -778,7 +778,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk)
 
 /* Set the clock rate for a clock source */
 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
 {
 	int ret = -EINVAL;
 	void __iomem * reg;
@@ -795,7 +794,7 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
 		validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 		if (validrate != rate)
-			return(ret);
+			return ret;
 
 		field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 		if (div_sel == 0)
@@ -837,8 +836,9 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 			wmb();
 		}
 		ret = 0;
-	} else if (clk->set_rate != 0)
+	} else if (clk->set_rate != 0) {
 		ret = clk->set_rate(clk, rate);
+	}
 
 	if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 		propagate_rate(clk);
@@ -872,10 +872,10 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			else if (src_clk == &core_ck)	/* divided clock */
 				val = 0x10;		/* rate needs fixing */
 		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
-			   cpu_is_omap2420()){
+			   cpu_is_omap2420()) {
 			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 			mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
-			if(src_clk == &func_96m_ck)
+			if (src_clk == &func_96m_ck)
 				val = 0;
 			else if (src_clk == &core_ck)
 				val = 0x10;