Commit e4b6c1fb authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren

omap2: fix clock.h rate_offset whitespace

Some of the .rate_offset lines in clock.h have whitespace problems;
fix them.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 22b40b82
...@@ -843,7 +843,7 @@ static struct clk iva1_ifck = { ...@@ -843,7 +843,7 @@ static struct clk iva1_ifck = {
.parent = &core_ck, .parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL | .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
.rate_offset= 8, .rate_offset = 8,
.enable_reg = (void __iomem *)&CM_FCLKEN_DSP, .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
.enable_bit = 10, .enable_bit = 10,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
...@@ -938,7 +938,7 @@ static struct clk gfx_3d_fck = { ...@@ -938,7 +938,7 @@ static struct clk gfx_3d_fck = {
RATE_CKCTL | CM_GFX_SEL1, RATE_CKCTL | CM_GFX_SEL1,
.enable_reg = (void __iomem *)&CM_FCLKEN_GFX, .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
.enable_bit = 2, .enable_bit = 2,
.rate_offset= 0, .rate_offset = 0,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -949,7 +949,7 @@ static struct clk gfx_2d_fck = { ...@@ -949,7 +949,7 @@ static struct clk gfx_2d_fck = {
RATE_CKCTL | CM_GFX_SEL1, RATE_CKCTL | CM_GFX_SEL1,
.enable_reg = (void __iomem *)&CM_FCLKEN_GFX, .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
.enable_bit = 1, .enable_bit = 1,
.rate_offset= 0, .rate_offset = 0,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment